Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 20

Fig. 1.20 Pass/fail boundary
(Shmoo Plot) for defect-free
silicon and with an
interconnect open resistance
of 1 and 3 M,( Kruseman
and Heiligers 2006 )

In some cases, high voltages are also used as voltage stress testing for reliabil-
ity screening ( Kawahara et al. 1996 ; Chang and McCluskey 1997 ; Aitken 2002 ) .
Stressing the device with high voltages may improve the detection of some defects.
This technique is particularly useful for detecting oxide thinnings and via defects,
which shorten device lifetime. The goal of stressing devices is to make these flaws
evident, causing via defects to become opens and oxide thinnings to become oxide
breaks. However, two parameters must be thoroughly controlled, i.e., power supply
voltage and stressing time. If any of these two parameters exceeds the allowed limit,
defect-free devices could be damaged.

Observation of quiescent current consumption of the circuit I DDQ mayalsobe
effective in technologies with reduced background leakage currents (i.e., low non-
defective I DDQ ). In these circumstances, the detection of interconnect open defects
may sometimes be possible although this technique is not as useful as for other types
of defects, such as bridges. The detection of open defects by I DDQ is strongly depen-
dent on cell design and circuit topology. Assuming an interconnect full open defect,
if an intermediate voltage is induced on the floating line, the two transistors driven
by the floating line may be in a conduction state, generating a current path from
V DD to GND, and thus resulting in extra current consumption ( Singh et al. 1995 ;
Champac and Zenteno 2000 ).
Temperature can also help to detect resistive opens. Assume, as a first approxi-
mation, that the open resistance is not modified with temperature. As temperature
decreases, the dominant effect is usually the increasing mobility, which decreases
the on resistance of transistors. In such situation, the relative importance of the de-
lay added by the defect increases. Hence, cold testing improves the observability of
resistive opens. However, the open resistance does vary with temperature as well.
Therefore, the delay induced by the open changes. The temperature coefficient of
the resistance depends on the resistive open material. Hence, the delay added by the
open may increase or decrease with temperature. In fact, resistive opens may pass
the test at nominal conditions, but can be detected at a temperature different from
the nominal one. For instance, the work of Needham et al. ( 1998 ) reported a resis-
tive open between an interconnect and a via causing a functional failure at 20 ı C,
which was not detected at room temperature.