Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 18

Tabl e 1. 3 Experimental results showing the history effect ( Arumı et al. 2008a )
Sequence of 0s and 1s

R O .100 k<R1<R2<R3<R4 < 100 M/

%1s R1 R2 R3 R4

100

90 d

80 d

70 d

60 d d

50 d d

40 d d

30 d d

20 d d

10 d d

0 d d d

The history effect must be minimized when performing a delay test. Otherwise,
resistive open defects may escape the test. For this reason, when a test is applied to a
specific target net in order to test for a rising (falling) transition, the net must remain
at a low (high) logic value for a sufficient number of cycles before the initialization
pattern is applied. In this way, it is assured that the target node covers the maximum
voltage excursion to reach its final logic state.
Finally, another factor is known to influence the detectability of resistive open
defects, i.e. the dynamic behavior of neighboring lines coupled to the defective line.
Figure 1.12 shows how the largest delay was obtained when the neighboring lines
underwent the opposite transition related to the defective line. In fact, the effective
capacitance between two nets depends on their state as well as on the skew between
the transitions generated on every line. Let us assume that C Ni is the capacitance be-
tween the neighboring line and the defective line when both lines are in a quiescent
state. In the case of a null skew, when a transition is generated in the defective line,

the effective capacitance C eff.Ni/ between the defective line and its neighboring
line N i can be approximated as follows ( Sakurai 1993 ):

<

0 for the same transition in N i
C Ni for N i in a quiescent state
2C Ni for the opposite transition in N i

C eff.Ni/ (1.8)

:

According to Eq. 1.8 , obtaining the largest delay caused by a resistive open defect
requires maximizing the total effective capacitances between the defective line and
its neighboring lines.
Although usually applied to resistive opens, delay considerations can also be
useful for interconnect full open defects. In nanometer technologies, it has been
shown how, in the presence of an interconnect full open defect due to the impact
of gate leakage currents, a transient evolution is induced in the floating line until it
reaches the steady state, which is determined by the technology and the topology
of the downstream gate(s). Experimental measurements show that these transient