Hardware Reference
In-Depth Information
Among the seminal approaches proposed concerning off-line testing (either ac-
count directly of the defects at electrical level for test generation or impose layout
rules so that the test generation can still be based on the stuck-at fault model), the
major developments made in the subsequent years have rather followed the first
approach. This is evidenced by the large body of work reported in other chapters.
The same concerns about fault representativeness apply in turn to the testing
techniques aimed at assessing the adequacy and efficiency of the fault tolerance
mechanisms meant to ensure the dependability of a computerized-system. Fault in-
jection testing - i.e., the explicit exposure of a fault-tolerant system to artificially
induced faulty situations - offers a pragmatic and now well-recognized approach
to test the fault tolerance mechanisms with respect to the specific inputs they are
intended to cope with: the faults. The extent to which the errors provoked by in-
jected faults match those induced by real faults is an essential dimension to ensure
the soundness of the inferences derived from a fault injection experiment. To il-
lustrate this issue we have described the main results of a series of experiments
meant to compare the errors induced by four injection techniques - namely, heavy-
ion radiation, pin-forcing, electromagnetic interference and SWIFI. Applying these
techniques to a common target system (a real time distributed fault-tolerant architec-
ture) using a common testbed, has allowed for a comprehensive and fair assessment.
The results show that, to a large extent, these techniques are complementary: they
provoke rather distinct distributions in the activation of the error detection mecha-
nisms included into the target system. Accordingly, their joint application is to be
recommended to increase the confidence in the evaluation of (i) the coverage pro-
vided by these mechanisms and (ii) the dependability properties of the target system.
In spite of such results and other related efforts, further research is still needed for
an improved characterization of the representativeness of the injected fault models.
Acknowledgment
The pioneering research reported in Section
8.2
was led by Christian Landrault
at LAAS-CNRS. Incidentally, it constitutes his first work on hardware testing, topic on which he
has eagerly contributed since then at LIRMM. We are really pleased that we have been given the
opportunity to participate in this way to this special book!
The authors would like to thank several colleagues and friends from EFCIS (now ST Micro-
electronics), ESPRIT project PDCS, IST project DBench and from IFIP WG 10.4 on Dependable
Computing and Fault Tolerance, for the fruitful exchanges along the years on the various topics
addressed in the Chapter. In particular, we are grateful to Alain Costes and Michel Diaz (LAAS-
CNRS), and also X. Messonnier, P. Rousseau, and Michel Vergniault (EFCIS) for their helpful
son and Peter Folkesson (Chalmers U.), Hermann Kopetz, G unther Leber and Emmerich Fuchs
(Vienna UT), for their contributions to the reflections carried out and to the comprehensive com-
parative study reported.
This work was supported in part by DRET, EFCIS, ESPRIT project PDCS, IST project DBench,
and IST network of excellence ReSIST.
In Memoriam.
Jacques Galiay, whose contribution to the work on offline testing was essential,
sadly deceased in the early 1980s, during a hike in the Alps mountains.
