Hardware Reference
In-Depth Information
Tabl e 8. 6
Properties of the fault injection techniques used
EI (with
SWIFI Compile
Properties
Heavy-ion
Pin-level
probe)
time
Reachability
High
Medium
Medium
Low to medium
Controllability
Low
High
Low
High
wrt space
Controllability
None
Low to
Low
Medium to
wrt time
medium
high
Repeatability
None to low
Medium to
high
None to low
High
Reproducibility
Medium to
high
High
Low
High
Non-
intrusiveness
Low
Medium
High
High
Time
measurement
Low to
medium
High
Low
Medium to high
Efficacy
High
High
High
Low
in scope, this analysis builds up on insights gained during the experiments carried
out on the MARS system.
The table shows that
reachability
and
controllability
properties exhibit rather
distinct ratings for each technique. Moreover, the rating of pin-level injection as
medium
and
high
with respect to reachability and space controllability is very much
dependent upon the integration level of the technologies of the ICs implementing
the target system. Indeed, recent highly integrated ICs would pose more problems
from these respects.
Recently, novel techniques have emerged that allow improving both reachability
while featuring a high level of controllability, including with respect to time. They
correspond to: (1) the scan chain-implemented fault injection technique, e.g., see
Aidemark et al.
(
2001
), that builds upon the testability-support capabilities featured
by most moderns VLSI devices and (2) FPGA-implemented fault injection tech-
nique (
de Andres et al.
2008
) that rely on the flexibility offered by FPGA devices to
fairly emulate a wide range of real hardware faults, including delay faults.
8.4
Summary
The representativeness of fault models with respect to real physical defects affecting
the manufacturing process or faults occurring in operation, is a major challenge
for the developers of dependable computer systems. In particular, as was clearly
physical defects could well be identified at the electrical diagram level, however
they could not be adequately accounted for by relying only on logical fault models
established at the gate level.
