Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 229

8.2.5.2 Implementation Rules for Detecting Unidirectional Errors

To make the detection of all the unidirectional errors feasible, the implementation of
the circuit should be inverter-free. This is impossible with MOS technology, because
all basic gates are inverting ones. Thus, unidirectional errors internal to the circuit
can induce multiple errors at the output.
As for single errors, the detection efficiency can be improved by means of im-
plementation rules, mainly targeting the supply lines. Using of the same principle
as the one proposed for single errors, it is possible to guarantee the detection of all
unidirectional errors induced by an open of a supply line. Conversely, as there ex-
ists no means of telling which gates can be affected by a threshold voltage drift, it
is impossible to detect all the unidirectional internal errors induced by such a fault
as they can finally produce a multiple error at the outputs of the circuit.

8.2.5.3 Implementation Rules for Detecting Multiple Errors

The detection of multiple errors is based on the use of the duplex paradigm, i.e.,
a structure made of two identical units performing the same task. With such a struc-
ture the detection of multiple errors affecting one of the two units is only ensured if
the two units are fault independent. For preventing a design fault (over-loaded gate
inducing a bad noise immunity) or a manufacturing defect to simultaneously affect
both units, it is desirable for the two units to be diversified (distinct implementa-
tions, one unit realized with normal logic and the other with complementary logic
( Crouzet et al. 1978 ; Crouzet and Landrault 1980 ).
When the two units are rigorously similar it is necessary to separate as much as
possible during the implementation those elements that have the same function in
the two units: so that a local degradation will not affect these elements.
As for the two previous cases, it is necessary that all opens of a supply line do
not affect both units without impacting the checker.

8.2.6 Concluding Remarks

It is recognized that the results presented are specific of the proposed example and
IC technology. However, regardless of this particular technology, one can retain the
proposed procedure and reproduce it for any circuit realized with any technology.
In that respect, note that Wadsack ( 1978 ) deals with fault modeling for the CMOS
technology.
To test a circuit, the first step must include an analysis of the failure mechanisms
of this circuit to obtain information about their nature and their probability. Then,
to facilitate test sequence generation, it is essential to derive a general model rather
than to individually consider all types of defects. However, as manufacturing pro-
cesses become more and more sophisticated, it appears that the stuck-at model, very