Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 222

V DD

Load
transistors

Gate 1 Gate 2 Gate 3

Contact-like
networks

V SS

Fig. 8.6 Rules at block level

R3 : Arrange any two adjacent gates to ensure that, if the output diffusion of the

one constitutes one of its external limits, then it adjoins a V SS diffusion of
the other gate.

Figure 8.6 illustrates rules 2 and 3.
All connections of each gate are enclosed in a domain bounded by the vertical
lines representing diffusions and the horizontal dotted lines. With such a layout,
the only possible short between two gates, for instance, gates numbered 1 and 2
on the figure always involve the output diffusion of the first and a V SS diffusion
of the second. This short can be modeled by a stuck-at-0 fault of the output of the
former.
Rules 4 and 5 are intended to control the short possibilities between the outputs
of two different gates (short #4 in Fig. 8.5 ) .

R4 : Arrange the gates of the block along a given direction in increasing level

order according to their logic level in the block.

R5 : Arrange the interconnections between the gates (which are realized by met-

allizations according to R1 to avoid shorts that can introduce asynchronous
sequential loops. For instance, given three interconnections A, B, and C, if a
short between A and B leads to a loop and shorts between A and C on one
hand and B and C on the other hand do not lead to a loop, then A and B can
be isolated by placing C between them. As a practical matter, this rule is not
very systematic, and therefore is not as easy to apply as R4 .

Gate Level We now describe rules for arrangements of equipotential lines within
a gate. First, remember that, according to R1 all connections in a gate are made by
diffusions.
For opens , as reported in Section 8.2.1 , most of the opens in a complex gate can
be modeled by stuck-at faults of either the output or one or more inputs of that gate.
For instance, for the gate of Fig. 8.3 a , only open #4 cannot be modeled by any stuck-
at fault because it leads to a modification of the logical function of the gate. Several
solutions are applicable for the layout. Figure 8.7 shows two of these possibilities
for the part of the gate related to inputs a, b c and d. With the first solution, open