Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 221

contact between a metallization of the upper level and a diffusion of the lower level
and thindowns corresponding to transistor gates.
The realization of diffusions and metallizations requires selective masking of
very precise regions on the surface of the chip. The inherent failure mode of such a
process consists of diffusing (or etching) regions that do not have to be diffused (or
etched) or vice-versa. On a manufactured chip, such defects involve shorts between
diffusions or metallizations and opens of diffusions or metallizations, only.
The growth of thick and thin oxide levels uniformly over the whole surface of the
chip implies homogeneous levels with relatively few defects. The thick oxide con-
stitutes a very good insulator between the diffusion level and the metallization level
and, as a consequence, shorts between a metallization and a diffusion are very un-
likely. Concerning the thin oxide, two kinds of defects can occur: local thindowns
enabling breakdown by electrostatic discharge, and local contamination involving
threshold voltage drift for the corresponding transistor. Electrostatic breakdown af-
fects mainly input and output buffers. It can be detected by parametric testing, and
more rarely affects transistors in the middle of the chip. Threshold voltage drift is a
gradual aging phenomenon and implies, at the logical level, that the concerned tran-
sistor is either off or on. This has the same effect as an open of the drain or source
diffusion or a short between these two diffusions.
Finally, for pin holes in the oxide, the only possible failure consists of a bad
contact between the diffusion and the metallization and acts as an open of one of
these connections.
Accordingly, an incomplete, but satisfactory fault coverage will be ensured for
monochannel MOS integrated circuits when considering the following two failure
assumptions: (A1) all possible defects consist of opens of diffusions or metalliza-
tions and shorts between two adjacent diffusions or metallizations, and (A2) No
short can involve a metallization and a diffusion.
It is worth noting that this evaluation qualitatively agrees with the experimental
results described in Section 8.2.1 .

8.2.3.2 Rules for Improving Testability

Block level. Using the failure assumptions defined above, we will first define five
layout rules governing the relative arrangement of gates. Rule 1 is based on failure
assumption A2. It aims at avoiding shorts between an internal connection between
the gates (short # 2 in Fig. 8.5 ) .

R1 : Make all internal gate connections entirely with diffusions and all intercon-

nections between gates entirely with metallization.
Rules 2 and 3 are intended to control the short possibilities between two
internal connections of two different gates (short #3 in Fig. 8.5 ) .

R2 : Arrange all internal gate connections (which are made by diffusions accord-

ing to rule 1) inside a domain whose external limits are either the output
diffusion or a V SS diffusion of this gate (the latter diffusion can be com-
monly used by two adjacent gates).