Hardware Reference
In-Depth Information
Fig. 8.5
Shorts in a block
1
structure
3
24
set that potential to V
SS
, and the transistors concerned are therefore always off.
The open will thus be detected while testing the gates including these transistors
if a low testing rate is assumed.
b.
The problem concerning shorts is more difficult. Figure
8.5
represents all types
of shorts occurring in the block structure. In addition to the shorts inside a gate
(1), there are shorts between a connection inside a gate and the output of this
or another gate (2), shorts between two internal connections belonging to two
different gates (3), and shorts between the outputs of two different gates (4).
Each of these shorts involves a specific erroneous behavior (introduction of asyn-
chronous sequential loop, modification of the function, introduction of analog
behavior, etc.). To determine suitable test sequences, these errors must be individu-
ally analyzed and, as the number of possible shorts is very high in LSI circuits, this
requires a very large amount of work.
Accordingly, it is more realistic to simplify the problem by reducing the number
of potential shorts and preferably removing those that are the most difficult to test,
based on restricting the circuit layout by a set of rules concerning arrangement of
the gates at the block level and of nodes at the gate level.
8.2.3
Improvement of Circuit Testability
The layout rules aimed at improving circuit testability are based on a set of failure
hypotheses that we will first justify by an analysis of the manufacturing process of
the technology used for the application circuit.
8.2.3.1
Manufacturing Process Analysis
Basically, a MOS chip consists of three interconnection levels (assuming an alu-
minum gate): (1) a lower level made by diffusions in an insulating substrate, (2)
an upper level made by metallizations, and (3) a medium level of oxide insulating
the two previous levels and presenting two kinds of discontinuities: holes enabling
