Hardware Reference
In-Depth Information
from the four processes. The timing unit furnishes real time clocks acting as internal
interrupts for the allocation unit. The remaining part of the circuit is composed of
three main blocks:
1.
The addressing system, composed of the incrementing array, the program coun-
ters, the output register A, and the buffers TP1 and TP2
2.
The processing unit, including the ALU, the accumulator Q, the input buffer DF,
the RAM M[R], and the condition test block
3.
The control block, including the sequencer and the supervisor
Pinpointing defects simply by direct observation of the chip is a very complex task.
Thus, to reduce the region of investigation, an initial step aimed at a prelocalization
of the failures was introduced. This specific test sequence is hierarchically organized
using a “start small” approach:
The total sequence is divided into subsequences each dedicated to the test of a
specific microprocessor block whose size is as small as possible.
The ordering of the subsequences is such that a fault detected by any of them
cannot be induced by one of the blocks tested by the previous subsequences.
The second step of the analysis consists of a direct observation of the chip in the re-
gion determined by the prelocalization sequence. Different techniques were applied:
1.
Parametric measurements, giving information about process quality
2.
Research of the shmoo plot domain (i.e., the domain of correct operation) for
different parameters, e.g., temperature, frequency, and supply voltage
3.
Visual inspection with an optical microscope
4.
Potential cartography with a scanning electron microscope
5.
Electrical analysis of the circuits nodes by placing probes onto the chip
This method has been applied to a set of 43 defective chips. The two main results
obtained from this study are as follows: (1) defects are randomly distributed and no
block is more vulnerable than any other, and (2) insights about the typical physi-
cal defect modes were derived. Table
8.1
depicts the observed defect modes. They
consist mainly of shorts and opens concerning either the metallizations or the dif-
fusions. It should be noted that no short was observed between metallization and
diffusion. For 10% of the cases, a logical error was clearly observed, but no defect
could be identified. For another 15%, the chips presented a very large imperfection
(e.g., a scratch from one side to the other of the chip) which can be considered as
Tabl e 8. 1
Observed failure
Short between metallizations
39%
modes
Open of a metallization
14%
Short between diffusions
14%
Open of a diffusion
6%
Short between metallization and substrate
2%
Non identified
10%
Non significant
15%
