Hardware Reference
In-Depth Information
as a general consequence, more effort will be required for the generation of the
test sequence. The list of faults must therefore be carefully selected to satisfy these
conflicting requirements: sufficient fault coverage and easy test generation.
Rather than considering each kind of physical defect of the circuit individually,
it is custom practice to deal with a more general fault model able to represent all of
them. At the time when the considered study was carried out, all testing approaches
were based on stuck-at-0 or stuck-at-1 of any connection of the logic diagram of the
circuit. Even if this model was relatively satisfactory for small-scale integration, it
was clearly no longer valid for large-scale integrated circuits. To tackle this problem,
we have first tried to carry out a characterization of LSI failure modes by analyzing
a set of failed circuits (
Crouzet et al.
1978
).
The considered application circuit is a 4-bit microprocessor designed by EFCIS
1
and realized with PMOS technology. It is able to manage four processes with dif-
ferent priorities, and it includes all the basic functions of an LSI IC: (1) scratchpad
memory, (2) arithmetic and logic unit, (3) program counters, and (4) control unit
realized with PLA. The internal architecture is based on a classical bus structure rep-
unit, and the timing unit. The allocation unit enables management of interruptions
NMST NHLT
NATG
4
4
VES
VALUES
TESTED
V
I
PC
SUPERVISOR
ALU
DC
FC
1
TV
RAM
M [R]
16 × 4
0
1
CONDITION
TESTS
5
4
1
R
SEQUENCER
TF
RI
Q
4
E(3-0)
COMMANDS
44
3
4
4
4
4
BI
4
DF
4
4
4
4
4
4
INCREMENTING ARRAY
+0, +1, +2
12
TP 1
TP 2
2
4
PROGRAM COUNTERS
RAM 4 × 12
A
LLOCATION
UNIT
TIMING
UNIT
12
4
4
4
4
4
NITR
NATG
A
A(11-0)
Fig. 8.1
Functional internal architecture of the application circuit
1
EFCIS:
Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux
, that has evolved to
form ST Microelectronics, in the late 1990s.
