Hardware Reference
In-Depth Information
Huang T-C, Lee K-J (1989) A token scan architecture for low power testing. In Proceedings of
international test conference, pp 660-669
Johnson DS, Aragon C, McGeoch L, Schevon C (1989) Optimisation by simulated annealing : an
experimental evaluation; part I, graph partitioning. Oper Res 37(865-892)
Lee K-J, Huang T-C, Chen J-J (Dec 2000) Peak-power reduction for multiple-scan circuits during
test application. In Proceedings of Asian test symposium, pp 453-458
Lee J, Touba NA (Oct 2004) Low power test data compression based n LFSR reseeding. In Pro-
ceedings of international conference on computer design, pp 180-185
Midulla I, Aktouf C (Dec 2008) Test power analysis at register transfert level. ASP J Low Pow
Electron 4(3):402-409
Najm F (Dec 1994) A survey of power estimation techniques in VLSI circuits. IEEE Trans VLSI
Sys 2(4):446-455
Nicolici N, Al-Hashimi B (2003) Power-constrained testing of VLSI circuits. Springer Science,
New York, NY
Pedram M, Rabaey J (eds) (2002) Power aware design methodologies. Kluwer Academic
Publishers
Pouya B, Crouch A (Oct 2000) Optimization trade-offs for vector volume and test power. In Pro-
ceedings of international test conference, pp 873-881
Rajski J, Tyszer J, Kassab M, Mukherjee N (May 2004) Embedded deterministic test. IEEE Trans
Computer-Aided Des 23:776-792
Ravi S, Devanathan VR, Parekhji R (Nov 2007) Methodology for low power test pattern generation
using activity threshold control logic. In Proceedings of international conference on computer-
aided-design, pp 526-529
Ravi S, Parekhji R, Saxena J (Apr 2008) Low power test for nanometer system-on-chips (SoCs).
ASP J Low Power Electron 4(1):81-100
Remersaro S, Lin X, Zhang Z, Reddy SM, Pomeranz I, Rajski J (Oct 2006) Preferred fill: a scalable
method to reduce capture power for scan based designs. In Proceedings of international test
conference, paper 32.2
Rosinger P, Gonciari T, Al-Hashimi B, Nicolici N (2001) Simultaneous reduction in volume of test
data and power dissipation for systems-on-a-chip. IEE Electron Lett 37(24):1434-1436
Rosinger P, Al-Hashimi B, Nicolici N (Jul 2004) Scan architecture with mutually exclusive scan
segment activation for shift- and capture-power reduction. IEEE Trans Computer-Aided Des
23(7):1142-1153
Roy K, Mukhopadhaya S, Mahmoodi-Meimand H (2003) Leakage current mechanisms and
leakage reduction techniques in deep-submicrometer CMOS circuits. In Proceedings of IEEE,
pp 305-327
Sankaralingam R, Oruganti R, Touba NA (May 2000) Static compaction techniques to control scan
vector power dissipation. In Proceedings of VLSI test symposium, pp 35-42
Sankaralingam R, Touba NA (Feb 2003) Multi-phase shifting to reducing instantaneous peak
power during scan. In Proceedings of Latin American Test Workshop, pp 78-83
Saxena J, Butler KM, Whetsel L (Oct 2001) A scheme to reduce power consumption during scan
testing. In Proceedings of internatinal test conference, pp 670-677
Saxena J, Butler KM, Jayaram VB, Kundu S, Arvind NV, Sreeprakash P, Hachinger M (Oct 2003)
A case study of ir-drop in structured at-speed testing. In Proceedings of international test con-
ference, pp 1098-1104
Sde-Paz S, Salomon E (Oct 2008) Frequency and power Correlation between At-Speed Scan and
Functional Tests. In Proceedings 39th IEEE international test conference (ITC) 2008, pp 13.3
Shi C, Kapur R (2004) How power aware test improves reliability and yield. IEEDesign.com,
Sep. 15
Wang Z, Chakrabarty K (Oct 2005) Test data compression for IP embedded cores using selective
encoding of scan slices. In Proceedings of international test conference, paper 24.3
Wang S, Gupta SK (Oct 1994) ATPG for heat dissipation minimization during test application. In
Proceedings of international test conference, pp 250-258
