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References
Altet J, Rubio A (2002) Thermal testing of integrated circuits. Springer Science, New York
Al-Yamani A, Chmelar E, Grinchuck M (May 2005) Segmented addressable scan architecture. In
Proceedings of VLSI test symposium, pp 405-411
Arabi K, Saleh R, Meng X (May-Jun 2007) Power supply noise in SoCs: metrics, management,
and measurement. IEEE Des Test Comput 24(3)
Athas WC, Svensson LJ, Koller JG, Tzartzanis N, Chin Chou EG (Dec 1994) Low-power digital
systems based on adiabatic-switching principles. IEEE Trans VLSI Sys 2(4):398-416
Badereddine N, Wang Z, Girard P, Chakrabarty K, Virazel A, Pravossoudovitch S, Landrault C
(Aug 2008) A selective scan slice encoding technique for test data volume and test power
reduction. JETTA J Electron Test - Theory Appl 24(4):353-364
Baik DH, Saluja KK (Oct 2005) Progressive random access scan: a simultaneous solution to test
power, test data volume and test time. In Proceedings of international test conference. Paper
15.2
Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (Nov 2001) A gated clock
scheme for low power scan testing of logic ics or embedded cores. In Proceedings of Asian
Test Symposium, pp 253-258
Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (Oct 2003) Efficient scan chain
design for power minimization during scan testing under routing constraint. In Proceedings of
international test conference, pp 488-493
Borkar SY, Dubey P, Kahn KC, Kuck DJ, Mulder H, Pawlowski SP, Rattner JR (2005) Platform
2015: Intel processor and platform evolution for the next decade. In Intel White Paper Platform
2015
Butler KM, Saxena J, Fryars T, Hetherington G, Jain A, Lewis J (Oct 2004) Minimizing power
consumption in scan testing: pattern generation and DFT techniques. In Proceedings of inter-
national test conference, pp 355-364
Chandra A, Chakrabarty K (Jun 2001) Combining low-power scan testing and test data compres-
sion for system-on-a-chip. In Proceedings of design automation conference, pp 166-169
Chandra A, Chakrabarty K (Jun 2002) Reduction of SOC test data volume, scan power and test-
ing time using alternating run-length codes. In Proceedings of design automation conference,
pp 673-678
Chang YS, Gupta SK, Breuer MA (Apr 1997) Analysis of ground bounce in deep sub-micron
circuits. In Proceedings of VLSI test symposium, pp 110-116
Cirit MA (Nov 1987) Estimating dynamic power consumption of CMOS circuits. In Proceedings
of international conference on computer-aided design, pp 534-537
Czysz D, Tyszer J, Mrugalski G, Rajski J (May 2007) Low power embedded deterministic test. In
Proceedings of VLSI test symposium, pp 75-83
Gerstendorfer S, Wunderlich HJ (Sep 1999) Minimized power consumption for scan-based BIST.
In Proceedings of international test conference, pp 77-84
Girard P, Guiller L, Landrault C, Pravossoudovitch S, Figueras J, Manich S, Teixeira P, Santos M
(1999) Low energy BIST design: impact of the LFSR TPG parameters on the weighted switch-
ing activity. In Proceedings of international symposium on circuits and systems, CD-ROM
Girard P, Guiller L, Landrault C, Pravossoudovitch S, Wunderlich HJ (May 2001) A modified clock
scheme for a low power BIST test pattern generator. In Proceedings of VLSI test symposium,
pp 306-311
Girard P (May-Jun 2002) Survey of low-power testing of VLSI circuits. IEEE Des Test Comput
19(3):82-92
Girard P, Wen X, Touba NA (2007) Low-power testing. In: Wang LT, Stroud CE, Touba NA (eds)
System-on-chip test architectures: nanometer design for testability. Morgan Kaufmann Pub-
lishers, pp 307-350
Hertwig A, Wunderlich HJ (May 1998) Low power serial built-in self-test. In Proceedings of Eu-
ropean test workshop, pp 49-53
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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