Models for Power-Aware Testing - Models in Hardware Testing - page 207

Tabl e 7. 5 Slice encoding with the 1-filling option

Slices Slice Codes

1 1 0 0 0 1 0 1 01 1000

11 0000

11 1100

11 0101

1 1 1 1 1 1 1 1 01 1000

1 0 0 1 1 1 1 1 01 1000

11 0000

11 1001

1 1 1 1 0 1 1 1 01 0100

19 Total WT

Consequently, test power considerations in this technique will consist in modify-
ing the initial selective encoding procedure by using one of the following X-filling
heuristics to fill don't-care bits:

0-filling: all Xs in the test sequence are set to 0s
1-filling: all Xs in the test sequence are set to 1s
MT-filling (Minimum Transition filling): all Xs are set to the value of the last
encountered care bit (working from the top to the bottom of column)

A counterpart of this positive impact on test power is a possible negative impact on
the test data compression rate. By looking at the results in Tables 7.4 and 7.5 , we can
notice that the number of slice-codes obtained after compression is 8 and 9 respec-
tively, which is much higher than 4 obtained with the original procedure (shown in
Tab le 7.2 ) . In fact, the loss in compression rate is much lower than it appears in this
example. Experiments performed on industrial circuits and reported in Badereddine
et al. ( 2008 ) have shown that test data volume reduction factors (12x on average)
are in the same order of magnitude than those obtained with the initial compression
procedure (16x on average). On the other hand, test power reduction with respect
to the initial procedure is always higher than 95%. Moreover, this method does not
require detailed structural information about the IP core under test, and utilizes a
generic on-chip decoder which is independent of the IP core and the test set.

7.7 Summary

Reliability, yield, test time and test costs in general are affected by test power con-
sumption. Carefully modeling the different types and sources of test power is a
prerequisite of power aware testing. Test pattern generation, design for test, and test
data compression have to be implemented with respect to their impacts on power.
The techniques presented in this chapter allow power restricted testing with mini-
mized hardware cost and test application time.