Models for Power-Aware Testing - Models in Hardware Testing - page 203

et al. 2004 ) to decompress the deterministic test cubes. However, rather than doing
random fill of each expanded test cube, the proposed scheme pushes the decompres-
sor into the self-loop state during encoding for low power fill.

7.6.1.3 Broadcast-Scan-Based Schemes

These power-aware TDC schemes are based on broadcasting the same value to mul-
tiple scan chains. Using the same value reduces the number of bits to be stored in
the tester memory and the number of transitions generated during scan shifting. The
main challenge is to achieve this goal without sacrificing the fault coverage and the
test time.
The segmented addressable scan architecture presented in Fig. 7.15 is an efficient
power-aware broadcast-scan-based TDC solution ( Al-Yamani et al. 2005 ) . Each
scan chain in this architecture is split into multiple scan segments thus allowing
the same data to be loaded simultaneously into multiple segments when compati-
bility exists. The compatible segments are loaded in parallel using a multiple-hot
decoder. Test power is reduced as segments which are incompatible within a given
round, i.e., during the time needed to upload a given test pattern, are not clocked.
Power-aware broadcast-scan-based TDC can also be achieved by using the
progressive random access scan (PRAS) architecture proposed in Baik and
Saluja ( 2005 ) that allows individual accessibility to each scan cell. In this ar-
chitecture, scan cells are configured as an SRAM-like grid structure using specific
PRAS scan cells and some additional peripheral and test control logic. Providing
such accessibility to every scan cell eliminates unnecessary switching activity dur-
ing scan, while reducing test time and data volume by updating only a small fraction
of scan-cells throughout the test application.

Clock Tree

Segment 1

Segment 2

￿
￿
￿

Segment
Address

Segment M

Tester Channel or
Input Decompressor

Fig. 7.15 The segmented addressable scan architecture