Models for Power-Aware Testing - Models in Hardware Testing - page 193

can significantly reduce average power consumption during scan shifting ( Butler
et al. 2004 ). Some of these fill options are available today in commercial ATPG
tools.
In the context of at-speed scan testing, X-filling solutions have also been pro-
posed to reduce capture power (and not necessarily shift power) and thus avoid IR-
drop-induced yield loss ( Wen et al. 2005 a ). These solutions were developed to pro-
vide power-aware launch-off-capture delay tests, and are based on estimation-based
X-filling ( Wen et al. 2006 b), probability-based X-filling ( Remersaro et al. 2006 ) ,
justification-based X-filling ( Wen et al. 2005 b ) or a mix of them ( Wen et al. 2007 ).
X-filling techniques have no impact on design flow and do not incur any area
overhead. On the other hand, they reduce test power sometimes at the expense of an
increase in pattern count (to achieve a given fault coverage) and they offer limited
gain for compressed patterns ( Ravi et al. 2008 ).

7.4.2 Test Generation for Low Energy BIST

A Linear Feedback Shift Register (LFSR) is a low-overhead structure commonly
used during BIST to generate and apply pseudo-random test patterns to the circuit
under test (CUT). Various low power LFSR-based test generators have been pro-
posed so far, such as (among others) the Dual-Speed LFSR-based generator ( Wa n g
and Gupta 1997 ) or the Low Transition Random Test Pattern Generator ( Wa n g a n d
Gupta 1999 ) . The main objective of these solutions is to reduce heat dissipation
during testing, which is achieved by reducing switching activity without increasing
test time.
Energy is another important dissipation parameter and represents the total
switching activity generated during application of the complete test sequence.
Beside issues as those described in Section 7.3 , an energy increased during BIST
has impact on the battery lifetime of battery operated devices, particularly those
equipped with on-line test facilities or those requiring self-test procedures during
power-up for system integrity checking (such as cellular phones).
In this section, we describe a study initially proposed in Girard et al. ( 1999 )to
analyze the impact of tuning LFSR parameters on the energy consumed during test.
A solution for low energy BIST generation is then proposed.

7.4.2.1 Impact of LFSR Parameters on Energy

The aim of LFSR tuning is to find a way of decreasing the energy consumed during
BIST by appropriately selecting the parameters of the LFSR, i.e., the seed and the
characteristic polynomial. However, the minimization problem, constrained by two
functions, Energy and Fault Coverage, may show different sensitivity to the vari-
ables under analysis (polynomial and seed). For this reason, two sub-problems were
considered: (i) impact of LFSR polynomial selection on energy, and (ii) impact of
LFSR seed selection on energy.