Models for Power-Aware Testing - Models in Hardware Testing - page 187

Concerning static power dissipation during test, there is no clear evidence that it
can be higher than static power in functional mode, except for I DDQ test (sensitivity
is reduced in this case) or burn-in test (the exponential dependence of sub-threshold
leakage on temperature leads to higher static power dissipation that can result in
thermal runaway condition and hence yield loss). Though depending on the logic
values of test patterns (but not on input transition or load capacitance), static power
dissipation does not necessarily increase during test. Modeling of static power dur-
ing test is similar to modeling of static power during functional mode.

7.2.3 Test Power Estimation

During conventional design, power consumption in functional mode is estimated
by using (i) architectural-level power estimation, (ii) RT-level power estimation,
and/or (iii) gate-level power estimation ( Najm 1994 ). Each one of these estimation
strategies represents different tradeoffs between accuracy and estimation time (see
Fig. 7.3 ) .
Estimation of test power consumption is not only required for sign-off (and avoid
destructive testing) but also to facilitate power-aware test space exploration (during
DFT or ATPG) early in the design cycle ( Ravi et al. 2008 ). However, as scan in-
sertion and test generation are commonly done at the gate level in today's design
flows, only gate-level estimators for test power are used in practice. Though accu-
rate, a limitation of gate-level estimation is that it prevents better decisions regarding
test power early in the design cycle. Moreover, these industrial estimators are often
simulation-based. Though manageable for small size circuits, this approach may
be impractical for multi-million gate SoCs as a complete simulation of ATPG test
patterns is too much time and memory consuming.
Quick and approximate models of test power have also been suggested in the
literature. The weighted transition metric proposed in Sankaralingam et al. ( 2000 )
is a simple and widely used model for scan testing, wherein transitions at flip-flops

Accuracy Estimation Time

Low Fast

Architecture-Level
Power Estimation

RT-Level Power
Estimation

Gate-Level Power
Estimation

Slow

High

Fig. 7.3 Accuracy versus time in power estimation