Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 7

Fig. 1.4 Transient response of the inverter with its input floating for the 90 nm PTM technology
( Arumı et al. 2008b ). ( a ) Inverter input and ( b ) inverter output. V FN0 is the initial input voltage

C gs(p)

I 1

C gb(p)

N 1 N 3 N m

C WELL

C N1 C N3 C Nm

I 3

C gd(p)

IN

Driving
gate

FN

OUT

C gd(n)

C SUBS

C N2

C gb(n)

N 2

I 2

C gs(n)

Fig. 1.5 Interconnect full open with the inclusion of the gate leakage currents ( Rodrıguez
et al. 2008 )

V DD ) are shown. A parasitic capacitance of 2 fF was assumed at the floating net.
A transient evolution until reaching the final steady state, which does not depend on
the initial voltage, is observed.
The time required for the defective inverter to reach the final steady state depends
on the technology, the initial voltage value, the total capacitance of the floating
node and the downstream transistors. Experimental results presented in the above
work showed that, for a 0:18 m technology, the transient evolutions were in the
order of seconds. However, simulation results demonstrated that these evolutions
were accelerated by several orders of magnitude for a 90 nm technology, being
in the order of a few s for a short net, as illustrated in Fig. 1.4 . It is expected
that these transient evolution times decrease even more as transistor dimensions are
scaled down.
For nanometer technologies, the electrical model traditionally reported (see
Fig. 1.3 ) is not accurate since the impact of gate leakage currents is ignored. These
currents can be modeled by voltage controlled current sources. Without loss of gen-
erality, consider the example in Fig. 1.5 , where the floating line is driving an inverter.