Hardware Reference
In-Depth Information
The power issues are severe in design and system mode, but they have been
seen earlier during design for test and in test mode ( Nicolici and Al-Hashimi 2003 ;
Girard 2002 ). Test has to exercise all devices of the circuit in short time, and, if
countermeasures are not taken, switching activity will be 2 to 4 times as high as in
the system mode ( Sde-Paz and Salomon 2008 ). The increased current may have im-
pact on the circuit's lifetime or may even damage it and the overstress may change
the circuit's behaviour and result in yield loss. The classical workaround in indus-
try consists in partitioning and scheduling the test ( Zorian 1993 ), reducing the test
frequency or even both. These measures will increase test time and incur additional
costs, and the reduced test speed makes it difficult to detect delay faults as described
in the previous chapters.
Power considerations during test are motivated by cost and reliability aspects.
The next section will describe appropriate models for power estimation during
functional mode and during test mode. While average power is related to heat dis-
sipation, instantaneous and peak power introduce additional robustness problems.
Modeling and estimating test power introduce also complexity issues as the exact
computation of the power consumption during scan shifting is rather expensive.
Section 7.3 discusses in detail the impact of test power on reliability, yield and
test costs. Automatic test pattern generation algorithms can take care of this to a
large extent; methods for supporting external and built-in testing during ATPG are
discussed in Section 7.4 .
Section 7.5 presents power-aware design for test solutions mainly for scan based
techniques. For systems-on-a-chip of today's size, test data compression and com-
paction are mandatory to limit test time and fulfil throughput requirements. Yet,
these techniques may introduce additional switching activity, if special precautions
are not taken as described in Section 7.6 .
7.2
Models for Power Estimation
As power consumption is now considered as a constraint during test, power estima-
tion is required to measure the saving in power and evaluate the effectiveness of a
given test power reduction technique. Models are needed for test power estimation.
In this section, we describe the models used to estimate the various components of
power consumption during functional mode and test mode. We also discuss how test
power can be estimated at the various levels of abstraction of the design process.
7.2.1
Functional Power Modeling
The main components of CMOS power consumption are from dynamic and static
sources. Dynamic power is typically defined as the power consumed whenever the
circuit is switching, while static power is the power consumed when the circuit is
idle ( Pedram and Rabaey 2002 ).
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