Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 6

C UP
C UP C C DOWN V DD C

Q o
C UP C C DOWN

V FL D (1.5)

From Eq. 1.5 it is derived that the voltage of the floating line is determined by
the ratio between the parasitic capacitances tied to the power supply .C UP /,and
the sum of all the parasitic capacitances tied to the power supply and to ground
.C UP C C DOWN /, plus the influence of the trapped charge.
However, in some cases, both V FL and V OUT may be set to intermediate voltages
not belonging to the digital domain. In such situations, V OUT depends on the exact
value of V FL and the logic interpretation of the defective line is more difficult to be
predicted.
Feedback capacitive paths may cause sequential behavior in some defective
circuits. Konuk and Ferguson ( 1998 ) reported that Miller and wire-to-wire capaci-
tances are the two types of capacitances responsible for these sequential behaviors.

Thin Open Defects

The behavior of interconnect full opens may vary depending on whether they have
a small (thin) or a large (thick) lack of conducting material ( Henderson et al. 1991 ;
Hawkins et al. 1994 ). A large open decouples completely the two end points of the
cavity created by the defect and its behavior is as reported in previous paragraphs.
Nevertheless, if the open is small, the distance between the two electrically discon-
nected points causes the non-conductive material in between to be very thin. In this
situation, electrons and holes are able to tunnel through, generating a slow charge
transfer, which increases the rise and the fall times of the signal to be propagated
through the line.

Open Defects with Gate Tunneling Leakage

Aggressive technology scaling trends have led to a significant increase in CMOS
transistor gate leakage due to the reduction in gate oxide thickness. In nanome-
ter technologies, high leakage current through the gate oxide is common in those
devices due to direct tunneling mechanisms. Gate tunneling leakage affects the
behavior of defective floating lines. The floating line cannot then be considered
electrically isolated as it is subjected to transient evolutions until reaching the steady
state, which occurs when the sum of all the gate leakage currents flowing into and
out of the floating node is zero. This condition is determined by technology param-
eters and the topology of downstream gate(s) ( Rodrıguez-Montanes et al. 2007b ) .
Arum´ıetal. ( 2008b ) presented some simulation results where this behavior was
observed. Figure 1.4 illustrates the SPICE simulation results corresponding to a
floating line driving an inverter for a 90 nm technology. The dynamic evolution due
to the impact of the gate leakage currents on the floating line .V FN / and the response
of the inverter .V OUT / for two initial voltages at the input node (V FN0 equals 0 and