Models in Memory Testing - Models in Hardware Testing - page 162

Fig. 6.10 Device level structural model of a 3 3 SRAM

improvement of silicon technology leading to an increased sensitivity to fabrication
defects and environmental stress.
Given this premise, a complete description of all proposed FFMs and related fault
mechanisms would be too long to fit a single book chapter. Moreover, the continuous
technology improvement would make it outdated in a short time. For this reason this
section will focus on the basic concepts and theories required to understand and to
work with memory FFMs, introducing a reduced set of well established FFMs, only.
According to the simplified RT-Level structural model proposed in Fig. 6.9 ,
FFMs can be classified according to the targeted functional block as: FFMs for