Models in Memory Testing - Models in Hardware Testing - page 161

Fig. 6.9 Simplified RT-Level
memory structural model

Moving down to the logic level, behavioral descriptions (Fig. 6.5 ) are usually ac-
complished resorting to Boolean expressions representing the Boolean function of
each output, whereas structural descriptions at the same level consist of netlists, i.e.,
interconnections of gates and/or flip-flops and latches. Since memories are very sel-
dom modeled resorting to their logic structures, the logic level is here of practical no
interest.More interesting for memories is the device level. Device level behavioral
models (Fig. 6.5 ) consist of descriptions of the electrical characteristics of the phys-
ical devices used to build the memory, i.e. voltage levels, currents, etc. with related
timings. Structural descriptions at the same level consist of proper interconnections
of the basic electrical components used to implement the memory, i.e., transistors,
resistors, capacitors, and connectors. Examples of structural descriptions of a typical
cells for SRAMs and DRAMs are in Fig. 6.3 a and b respectively, whereas Fig. 6.10
shows the complete structure of a 3 3 cells SRAM.

6.4 Fault Models

Fault modeling is probably one of the most important elements of memory test-
ing and fault analysis. As physical examination of memory is usually too complex,
test engineers resort to functional fault models (FFM) to build efficient functional
test algorithms. Functional test makes the proof of both test completeness and non-
redundancy a logic problem easy to manage and automate.
Fault modeling for memory has a long history. Early work on FFMs for RAMs
was done by Thatte and Abraham ( Thatte et al. 1977 ) followed by Van de Goor in
the early 1980s ( Ven de Goor et al. 1990 ) . These publications represent the basis
for more than 20 years of work in defining different types of FFMs and correspond-
ing test algorithms. This huge amount of work was motivated by the continuous