Models in Memory Testing - Models in Hardware Testing - page 160

Fig. 6.8 Detailed RT-Level memory structural model

terms of complexity (number of states equal to 2 # me morycells ), very small portions
of memories are usually represented and the memory regularity is then exploited to
properly extend the model.
RT-level structural descriptions (Fig. 6.5 ) play a significant role in testing-
oriented memory modeling. Memories are here modeled as a proper interconnection
of interacting sub-systems, each characterized by a specific function, and coop-
erating to achieve the target external memory behavior. Figure 6.8 shows the
detailed RT-level structural model of an SRAM proposed by Van de Goor in Va n
de Goor ( 1991 ). The memory cell array is the kernel of the memory and contains
the set (or “array”, or “matrix”) of memory cells, properly arranged in rows and
columns. To access each cell, the cell address is first partitioned to obtain the row
address and column address and then decoded by the row and column decoders.
The outputs of these two decoders are usually referred to as word lines (WLs) and
column selects (CSs), respectively. The address buffer, data-in buffer, and data-out
buffer store the addresses and data, while the sense amplifiers allow identifying the
data stored in the cells of the memory cell array.
When the memory model is used for test purpose, without exploiting the ac-
tual internal memory structure, the model of Fig. 6.8 is usually simplified as in
Fig. 6.9 ( Van de Goor 1991 ), where the address decoder and the read/write logic in-
clude all the logic required to perform address decoding and read/write operations,
respectively.