Hardware Reference
In-Depth Information
Fig. 6.4
Different memory modeling levels proposed by Van de Goor
Fig. 6.5 Abstraction level vs.
representation domain
modeling sub-space
a set of well established models used to represent memory structures, behaviors, and
architectures. In particular we shall focus on those models usually used in memory
testing.
The system level is the highest representation level and is usually very close to the
specifications. When dealing with memories, behavioral descriptions at system level
describe the memory behavior in terms of Input/Output (I/O) relationships. Timing
diagrams can be used to graphically represent the minimum and maximum timing
constraints and the I/O signal relationships for the various memory operations. On
the other hand, a system level structural model focuses on the definition of the I/O
signals of the memory. Figure 6.6 shows an example of (a) a single-port and (b) a
two-ports system level structural model.
Moving to the RT abstraction level, behavioral modeling is usually accomplished
resorting to state transition graphs (STG). STG based descriptions for memories,
first introduced in Brzozowski et al. ( 1992 ), have been used for long time to
 
 
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