Models in Memory Testing - Models in Hardware Testing - page 153

Chapter 6
Models in Memory Testing
From Functional Testing to Defect-Based Testing

Stefano Di Carlo and Paolo Prinetto

Abstract Semiconductor memories have been always used to push silicon
technology at its limit. This makes these devices extremely sensible to physical
defects and environmental influences that may severely compromise their correct
behavior. Efficient and detailed testing procedures for memory devices are therefore
mandatory. As physical examination of memory designs is too complex, working
with models capable of precisely representing memory behaviors, architectures, and
fault mechanisms while keeping the overall complexity under control is mandatory
to guarantee high quality memory products and to reduce the overall test cost. This
is even more important as we are fully entering the Very Deep Sub Micron era. This
chapter provides an overview of models and notations currently used in memory
testing practice highlighting challenging problems waiting for solutions.

Keywords Memory testing Memory modeling Fault models March test

6.1 Introduction

Since 1945 when the ENIAC, the first computer system with its memory of mercury
and nickel wire delay lines went into service, through the relatively expensive core
memory used in about 95% of computers by 1976, memory has played a vital role
in the history of computing.
With the advent of semiconductor memories for commercial applications (the
Intel TM 1103 shown in Fig. 6.1 was the first 1 Kbit dynamic RAM commercial chip),
for the first time a significant amount of information could be stored on a single chip.
This represented the basis for modern computer systems.

) and P. Prinetto
Politecnico di Torino, Control and Computer Engineering Department, Corso duca degli Abruzzi
24, 10129, Torino, Italy
e-mail: [e-mail]

S. Di Carlo (