Hardware Reference
In-Depth Information
Hora C, Segers R, Eichenberger S, Lousberg M (2002) An effective diagnosis method to sup-
port yield improvement. In Proceedings 33rd IEEE international test conference (ITC) 2002,
pp 260-269, doi:10.1109/TEST.2002.1041768
Keller BL (Aug 1996) Hierarchical pattern faults for describing logic circuit failure mechanisms,
US Patent 5,546,408
Khursheed S, Rosinger P, Al-Hashimi BM, Reddy SM, Harrod P (2008) Bridge defect diagno-
sis for multiple-voltage design. In Proceedings 13th European Test Symposium (ETS) 2008,
pp 99-104, doi:10.1109/ETS.2008.14
Klein R, Piekarz T (2005) Accelerating functional simulation for processor based designs.
Proceedings International Workshop on System-on-Chip for Real-Time Applications 2005,
pp 323-328, doi:10.1109/IWSOC.2005.34
Krstic A, Wang L-C, Cheng K-T, Liou J-J, Abadir MS (2003) Delay defect diagnosis based upon
statistical timing models - the first step. In Proceedings 6th Design, Automation and Test in
Europe (DATE) 2003, pp 10,328-10,335
Kundu S, Sengupta S, Goswami D (Apr 2006) Generalized fault model for defects and circuit
marginalities, US Patent 7,036,063
Lavo DB, Chess B, Larrabee T, Hartanto I (1998) Probabilistic mixed-model fault diagno-
sis. In Proceedings 29th IEEE international test conference (ITC) 1998, pp 1084-1093,
doi:10.1109/TEST.1998.743308
Li C-MJ, McCluskey EJ (2005) Diagnosis of resistive-open and stuck-open defects in dig-
ital CMOS ICs. IEEE Trans CAD Integrat Circuits Sys 24(11):1748-1759, doi:10.1109/
TCAD.2005.852457
Liu C, Zou W, Reddy SM, Cheng W-T, Sharma M, Tang H (Oct 2007) Interconnect open defect di-
agnosis with minimal physical information. In Proceedings 38th International Test Conference
(ITC) 2007, pp 7.3, doi:10.1109/TEST.2007.4437580
Liu C, Cheng W-T, Tang H, Reddy SM, Zou W, Sharma M (Nov 2008) Hyperactive faults dictio-
nary to increase diagnosis throughput. In Proceedings 17th Asian test symposium (ATS) 2008,
pp 173-178, doi:10.1109/ATS.2008.16
McPherson JW (2006) Reliability challenges for 45 nm and beyond. In Proceedings 43rd Design
Automation Conference (DAC) 2006, pp 176-181, doi:10.1145/1146909.1146959
Polian I, Czutro A, Kundu S, Becker B (Oct 2006) Power droop testing. In Proceedings inter-
national conference on computer design (ICCD) 2006, pp 243-250, doi:10.1109/ICCD.2006.
4380824
Pomeranz I, Reddy SM (1992) On the generation of small dictionaries for fault location. In Pro-
ceedings IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 1992,
pp 272-279, doi:10.1109/ICCAD.1992.279361
Riley M, Chelstrom N, Genden M, Sawamura S (Oct 2006) Debug of the CELL processor: moving
the lab into silicon. In Proceedings 37th IEEE international test conference (ITC) 2006, pp 26.1,
doi:10.1109/TEST.2006.297671
Rodrıguez-Monta nes R, Arumı, D, Figueras J, Eichenberger S, Hora C, Kruseman B (2007) Im-
pact of gate tunnelling leakage on CMOS circuits with full open defects. Electron Lett 43(21):
1140-1141, 11. doi:10.1049/el:20072117
Rousset A, Bosio A, Girard P, Landrault C, Pravossoudovitch S, Virazel A (Oct 2007) Fast bridging
fault diagnosis using logic information. In Proceedings 16th Asian Test Symposium (ATS)
2007, pp 33-38, doi:10.1109/ATS.2007.75
Roy K, Mak TM, Cheng K-T (2006) Test consideration for nanometer-scale CMOS circuits. IEEE
Des Test Comput 23(2):128-136, doi:10.1109/MDT.2006.52
Soden JM, Treece RK, Taylor MR, Hawkins CF (Aug 1989) CMOS IC stuck-open-fault electrical
effects and design considerations. In Proceedings 20th international test conference (ITC) 1989,
pp 423-430, doi:10.1109/TEST.1989.82325
Tirumurti C, Kundu S, Sur-Kolay S, Chang Y-S (2004) A modeling approach for addressing power
supply switching noise related failures of integrated circuit. In Proceedings 7th Design, Au-
tomation and Test in Europe (DATE) 2004, pp 1078-1083, doi:10.1109/DATE.2004.1269036
