Generalized Fault Modeling for Logic Diagnosis - Models in Hardware Testing - page 147

Fig. 5.7 Circuit model for
fault simulation

f 1 f 2

a

1

x

f 4

f 3

&

y

b

Tabl e 5. 3 Syndrome and
result from stuck-at fault
simulation

Pattern Syndrome f 1 f 2 f 3 f 4

ab xy xy xy xy xy

00 10 0 0 10 10 10

01 10 01 10 10 10

10 1 0 00 1 0 0 1 00

11 01 01 10 01 0 0

Tabl e 5. 4 Evidences and
rank of the four faults

Fault T T T T Rank

f 1 0 3 1 0 4

f 2 1 2 0 0 1

f 3 0 1 1 0 2 or 3

f 4 0 1 1 0 3 or 2

Now, the four faults are simulated for the given pattern set and their signatures
are shown in the remaining columns in Table 5.3 . The fault f 1 is observable in three
response bits, but it fails to explain the erroneous bit in the syndrome. This leads for
this fault to an evidence of e.f 1 ;T/ D . T ; T ; T ; T / D .0;3;1;0/. The evidence
is derived for the other stuck-at faults as well; Table 5.4 shows the result.
All evidences show T D 0, so the ranking procedure continues with T .Only
f 2 has positive T , so this fault is ranked above all other faults. The other faults are
ranked by increasing T . The top-ranked evidence f 2 shows positive T and positive
T . Therefore, none of the simulated faults can explain the syndrome completely, but
f 2 explains a subset of all fails. This leads to a CLF of the form a ˚ Œa cond with
some arbitrary condition.

5.4.4 Volume Diagnosis and Pattern Generation

If the resolution provided by the evidences of a test pattern set T is not sufficient dur-
ing adaptive diagnosis or design debug, we have the option to use the evidences for
guiding further diagnostic ATPG. In volume diagnosis, the pattern set is fixed, and
we have to extract as much diagnostic information as possible from rather limited
information. Usually, only the first i failing patterns are recorded, and in addition,
all the passing patterns up to this point can be used for diagnosis.