Generalized Fault Modeling for Logic Diagnosis - Models in Hardware Testing - page 146

Tabl e 5. 2 Fault models and
evidence forms

Classic model T T T

Single stuck-at 0 0 0

Stuck-at, more fault sites present 0 >0 0

Single conditional stuck-at >0 0 0

Cond. stuck-at, more fault sites
present

>0 >0 0

Delay fault, i.e. long paths fail >0 0 >0

This fault model independent pattern analysis approach is able to identify circuit
parts containing arbitrary faulty behavior. However, if the behavior of the DUD can
be explained using some classic fault models, certain evidence forms are observed.
Tab le 5.2 shows suspect evidences for some classic models.
If T , T and T are all zero, a single stuck-at fault explains the DUD behavior
completely. If T and T are zero, a faulty value on a single signal line under some
patterns T 0 T provides complete explanation. With T D T D 0, such a stuck-at
fault explains a subset of all fails, but some other faulty behavior is present in the
DUD. These other fault sites are independent from the stuck-at fault at hand, i.e.
for each pattern an output is either influenced by the stuck-at fault only or by some
other fault sites. With only T D 0, a faulty value on the corresponding single signal
line explains a part of DUD behavior and more fault sites are present again. If only
T is zero, the suspect fails are a superset of DUD fails.
If all suspects show positive values in all components T , T , T , the responses
were caused by multiple interacting fault sites, and all simplistic fault models would
fail to explain the DUD behavior.
For further analysis, the evidences in the knowledge base are ordered to create a
ranking with the most suspicious fault sites at the beginning (lowest rank). Firstly,
evidences are sorted by increasing T ,i.e.

T > T ) rank.e.f a ;T// > rank.e.f b ;T//

moving single conditional stuck-at faults in front. Evidences with identical T are
sorted by decreasing T moving candidates in front, which explain most failures:

T > T ) rank.e.f a ;T// < rank.e.f b ; T //:

Finally evidences with identical T and T are ordered by increasing T values:

T > T ) rank.e.f a ;T// > rank.e.f b ; T //:

For a brief example of the pattern analysis approach, consider the circuit in Fig. 5.7 .
It contains two gates and four exemplary stuck-at faults for fault simulation.
The exhaustive test set and the response from the DUD are shown in the first two
columns of Table 5.3 . The erroneous bits are shown in bold, the DUD has failed on
output x in the third pattern.