Hardware Reference
In-Depth Information
4.5.2
Feedback Faults
A bridging fault may involve two circuit lines with a sensitized path between these
lines, e.g., lines f and z in Fig. 4.2 . If the number of inverting gates on that path is
odd, the circuit may oscillate for some bridge resistances. Suppose that the value on
line v in Fig. 4.2 is 0 and that the fault-free values on lines f , w and z are 1, 0 and
0, respectively. For a given R sh value, the bridge between lines f and z will impose
an intermediate voltage V f .R sh / on line f . For some bridge resistance, V f .R sh /
could fall below the threshold of NAND gate F and will be interpreted as logic-0.
As a consequence, lines w and z will change their value to logic-1. This, in turn,
will bring the voltage on line f back to V DD , which will be interpreted as logic-1
by gate F .Lines w and z will thus oscillate between logic-1 and logic-0 with high
frequency.
In general, a test pattern applied to a circuit having a feedback bridging defect
with a given resistance could result in one of three possible circuit behaviors: either
impose a faulty value on at least one circuit output; or lead to oscillation observable
at an output; or have no effect. In the first case, the defect is detected; in the last case
the defect is not detected. Whether the defect is detected if it implies oscillation
depends on the characteristics of the automatic test equipment used. It is possible to
calculate the resistance intervals for which oscillation takes place, similar to ADIs
( Polian 2005 ) . If the automatic test equipment detects oscillation, these intervals can
be added to C-ADI and thus taken into account when calculating fault coverage.
Accurate calculation of resistance intervals for which the circuit exhibits oscilla-
tion is highly non-trivial. There are a variety of counter-intuitive situations in which
oscillation could take place, including feedback loops not sensitized in the fault-free
circuit ( disabled loops ). As a remedy, it is possible to pessimistically assume oscil-
lation for all resistance ranges which cannot be resolved accurately [ Polian 2005 ].
4.5.3
Dynamic Effects
This chapter concentrated on static effects of resistive bridging defects. All interme-
diate voltages are calculated in equilibrium, i.e., under assumption that the circuit is
given sufficient time to stabilize. A resistive bridging defect typically slows down
the switching speed of the gates driven by the bridged lines. A defect may not result
in an intermediate voltage erroneously interpreted by a succeeding gate and thus be
excluded from C-ADI. Yet the same defect could delay a transition at the succeed-
ing gate. If the defect-induced extra delay prevents the circuit from completing the
calculation of the output values within the clock cycle, the circuit will fail.
The dynamic effects of resistive bridging faults belong to the class of delay
faults . While delay faults are broadly covered in Chapter 3 , some simulation meth-
ods concentrate on delay faults induced by resistive bridging defects ( Li 2003 ;
Wang 2004 ). Similar to simulation of static RBF effects described above, the simu-
lation of dynamic effects consists of two components: accurate analysis on the fault
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