Fault Modeling for Simulation and ATPG - Models in Hardware Testing - page 121

Fig. 4.5 Automatic test pattern generation algorithm for resistive bridging faults

avoids unnecessary generation of sectioning information by producing the list of
critical resistances only for RBFs that are targeted explicitly in Line (7). No section-
ing will be performed for a fault covered by a test pattern generated for a different
fault in Line (20). If sectioning-based fault simulation is performed, critical resis-
tances will be computed ahead of time for all faults and their repeated calculation in
Line (7) can be omitted.
The algorithm terminates when the last fault has been dropped, i.e., ADIs L f are
empty for all faults. The ADIs G.f / are equal to G-ADI in the end: they consist
exclusively of sections for which no test pattern could be generated.

4.4.3 Experimental Results

Procedure RBF AT P G has been implemented and applied to 10,000 faults in IS-
CAS circuits. Table 4.4 summarizes the results for the largest circuits. The number
of RBFs undetectable for any R sh values, the number of generated test patterns, the
number of sections identified as undetectable and the run time on a 2 GHz Linux
machine with 2 GB RAM are reported.