Fault Modeling for Simulation and ATPG - Models in Hardware Testing - page 115

For a fixed FSIC and a fixed section, the behavior of the defective circuit can be
represented by a multiple stuck-at fault (i.e., a number of stuck-at faults simultane-
ously present in the circuit). Consider again the circuit from Fig. 4.2 , FSIC 0111 and
section [0, R D 0 ]. Gates C and D interpret the erroneous logical value of 0, while
gate E interprets the erroneous logical value of 1. Recall that this holds for any
defect with R sh 2 Œ0; R D 0 . This behavior is represented by a triple stuck-at fault:
stuck-at-0 at lines c and d and stuck-at-1 at line e. We denote this multiple stuck-at
fault by f c/0, d /0, e/1 g .
In sections [R D 0 , R C ]and[R C , R E 0 ], the equivalent multiple-stuck-at fault un-
der FSIC 0111 is f c/0, e/1 g . It is important that these sections are treated separately
even though the critical resistance R C has been calculated under a different FSIC
(0011). In section [R E 0 , R C 0 ], the equivalent fault is actually the single stuck-at
fault f c/0 g .Insection[R C 0 , R E ] there is no equivalent fault: the circuit behaves as
in the defect-free case.
The equivalent multiple-stuck-at fault does depend on the FSIC. Under FSIC
0011, the equivalent fault matches its counterpart under FSIC 0111 for section [R D 0 ,
R C ]: f c/0, e/1 g . However, in section [0, R D 0 ] the equivalent fault is f c/0, e/1 g (and
not f c/0, d /0, e/1 g as under FSIC 0111), and in section [R C , R E 0 ] the equivalent
fault is f e/1 g and not f c/0, e/1 g . This implies that there is generally no such thing as
a multiple stuck-at fault or a set of multiple stuck-at faults equivalent to an RBF. The
logical behavior of the defective circuit is dependent from both the defect resistance
(or section it belongs to) and the FSIC.

4.3.2 Sectioning-Based Simulation

The boundaries of any ADI which shows up in the interval-based simulation are
critical resistances. This is because only critical resistances are possible as the right
boundaries R i of local ADIs [0, R i ] when they are created at the fault site and all
transformations of an ADI during propagation (complementation, intersection and
merging) can only introduce a boundary of an existing ADI as a boundary of a new
ADI. As a consequence, each ADI can be represented as a union of sections.
Tab le 4.2 contains the normalized ADIs calculatedbyinterval-basedRBFsimu-
lation (explained in detail in the previous section) and the logical values assumed in
five considered sections. Note that the resistances which exceed the maximal crit-
ical resistance R max (range [R E 0 , 1 ] in the example) are not considered because
defects with these resistances are known to be undetectable. It is obvious that the
information on the logical values is sufficient to reconstruct the ADI by merging all
sections where the logical value of 1 is assumed. For example, the ADI on line w is
obtained as Œ0; R D 0 [ ŒR D 0 ;R C [ ŒR C ;R E 0 D Œ0; R E 0 , which is the correct
ADI determined by the interval-based simulation. In particular, the accurate ADI is
computed for the circuit output z .
Sectioning-based RBF simulation determines the sections and performs, for each
section, the simulation for an RBF restricted to that section. In the end, all sections