Fault Modeling for Simulation and ATPG - Models in Hardware Testing - page 114

4.2.5 Summary

Interval-based resistive bridging fault simulation is a relatively straightforward
method to compute the coverage of resistive bridging faults in the circuit by a test
set. It is based on an accurate local electrical analysis (described in Chapter 2 )which
yields intervals of bridge resistances called ADIs, and the propagation of the ADIs
to the outputs. During propagation, ADIs may change their shape: they can be elimi-
nated, inverted, intersected, or even get “holes” to become a disjoint set of intervals.
This algorithm can be applied to moderately sized circuits of a few tens or hundred
thousand gates. Experiments suggest that, out of the four alternative fault coverage
metrics, P-FC is least useful. E-FC and O-FC provide reasonably tight bounds for
the exact metric G-FC which, in general, requires information produced by resistive
bridging fault ATPG (described later in this chapter).

4.3 High-Performance Fault Simulation

Interval-based resistive bridging fault simulation is computationally intensive com-
pared to stuck-at fault simulation. A main reason for this is the complexity to store
and process the resistance intervals. In contrast, a variety of successful speed-up
techniques for stuck-at fault simulation relies on the efficient representation of logi-
cal values which show up during simulation. In this section, we present an approach
which enables some of these techniques in context of RBF simulation. The ap-
proach is based on restricting an RBF to a small resistance range called section
( Shinogi 2001 ). An RBF restricted to a section has properties similar to a multiple
stuck-at fault. We demonstrate significant speed-ups for academic benchmark cir-
cuits of moderate size and applicability of the approach to industrial multi-million
gate designs without any loss of accuracy.

4.3.1 Sectioning

GivenanRBF,let0 DW R 0 <R 1 < ::: < R m be the sorted list of all its critical
resistances. Note that R m corresponds to R max defined in Section 4.1 of this chapter.
A section is a resistance interval [R i 1 , R i ] bounded by two critical resistances and
containing no further critical resistance. For all defects with resistance from the
same section, a gate driven by a bridged line will interpret the same value. (If a
gate interprets logic-0 for one defect resistance and logic-1 for a different defect
resistance, there must be a critical resistance between these resistances, so these
resistances cannot be from the same section.) Hence, there exists the detection status
of an RBF restricted to a section: either all defects with resistance from the section
are detected by a test pattern, or no such defect is detected.