Hardware Reference
In-Depth Information
Pomeranz I, Reddy SM (Feb 1994) An efficient non-enumerative method to estimate the path delay
fault coverage in combinational circuits. IEEE Trans Comput-Aided Des Integrat Circuits Sys
13:240-250
Pomeranz I, Reddy SM (Nov 1995) Functional test generation for delay faults in combinational
circuits. Proceedings of international conference on computer-aided design, pp 687-694
Pomeranz I, Reddy SM, Uppaluri P (Dec 1995) NEST: a non-enumerative test generation method
for path delay faults in combinational circuits. IEEE Trans Comput-Aided Des Integrat Circuits
Sys 14:1505-1515
Pomeranz I, Reddy SM (Jan 1996a) On the number of tests to detect all path delay faults in com-
binational logic circuits. IEEE Trans Comput-Aided Des Integrat Circuits Sys 15:50-62
Pomeranz I, Reddy SM, Patel JH (Mar 1996b) On double transition faults as a delay fault model.
Proceedings of Great Lakes symposium on VLSI, pp 282-287
Pomeranz I, Reddy SM (1998) Delay fault models for VLSI circuits. Integrat VLSI J 26:21-40
Pomeranz I, Reddy SM (Sep 2002) On the coverage of delay faults in scan designs with multiple
scan chains. Proceedings of international conference on computer design: VLSI in computers
and processors, pp 206-209
Pomeranz I, Reddy SM (Oct 2006) Generation of functional broadside tests for transition faults.
IEEE Trans Comput-Aided Des Integrat Circuits Sys 25:2207-2218
Pomeranz I, Reddy SM (Jan 2008) Transition path delay faults: a new path delay fault model for
small and large delay defects. IEEE Trans VLSI Sys 16:98-107
Pomeranz I, Reddy SM (Jan 2008) Unspecified transition fault model: a transition fault model for
at-speed fault simulation and test generation. IEEE Trans Comput-Aided Des Integrat Circuits
Sys 27:137-146
Pomeranz I, Reddy SM (Jan 2009) Functional broadside tests under an expanded definition
of functional operation conditions. IEEE Trans Comput-Aided Des Integrat Circuits Sys
28:121-129
Pomeranz I, Reddy SM (2009) Hazard-based detection conditions for improved transition fault
coverage of scan-based tests. IEEE Trans VLSI Sys 17
Pramanick AK, Reddy SM (Sep 1989) On the detection of delay faults. Proceedings of interna-
tional test conference, pp 680-687
Pramanick AK, Reddy SM (Mar 1990) On the fault coverage of gate delay fault detecting tests.
Proceedings of European Design Automation Conference (EDAC), pp 334-338
Pramanick AK, Reddy SM (Jan 1997) On the fault coverage of gate delay fault detecting tests.
IEEE Trans Comput-Aided Des Integrat Circuits Sys 16:78-94
Rearick J (Oct 2001) Too much delay fault coverage is a bad thing. Proceedings of international
test conference, pp 624-633
Reddy SM, Pomeranz I, Kajihara S, Murakami A, Takeoka S, Ohta M (Oct 2000) On validating
data hold times for flip-flops in sequential circuits. Proceedings of international test conference,
pp 317-325
Rosinger P, Al-Hashimi BM, Nicolici N (Jul 2004) Scan architecture with mutually exclusive scan
segment activation for shift-and-capture-power reduction. IEEE Trans Comput-Aided Des In-
tegrat Circuits Sys 23:1142-1153
Sato Y, Hamada S, Maeda T, Takatori A, Kajihara S (Jan 2005) Evaluation of the statistical
delay quality model. Proceedings of Asia and South Pacific design automation conference,
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Savir V, Patil S (Aug 1993) Scan-based transition test. Trans Comput-Aided Des Integrat Circuits
Sys 12:1232-1241
Savir J, Patil S (Aug 1994) Broad-side delay test. Trans Comput-Aided Des Integrat Circuits Sys
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Saxena J, Butler KM, Jayaram VB, Kundu S, Arvind NV, Sreeprakash P, Hachinger M (Sep 2003)
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sidering operating conditions. Proceedings of European test symposium, pp 54-59
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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