Models for Delay Faults - Models in Hardware Testing - page 96

segments. All segments share one scan-in and one scan-out lines. Each segment
can thus be loaded and unloaded independently while the other segments are inac-
tive. This reduces the switching activity during scan loads and unloads. Also if each
segment can be independently clocked each segment can independently capture thus
permitting reduced switching activity in capture cycles ( Rosinger et al. 2004 ). The
clocks and the tri-state buffers at scan-outs are controlled through additional logic as
shown in Fig. 3.26 . In Lee et al. ( 2004 )and Rosinger et al. ( 2004 )itwasshownthat
stuck-at fault coverage for segmented scan designs is the same as for the correspond-
ing unsegmented scan designs. However the number of test patterns could be lower
for segmented designs using appropriate test generation procedures ( Zhang 2006 b ).
For some circuits segmented designs may require fewer stuck-at patterns than the
minimum possible number of test patterns for the corresponding unsegmented de-
sign ( Zhang 2006 b). As for delay faults, segmented scan designs may have higher
fault coverage, as discussed below, due to the fact that many different combinations
of launch and capture in different segments can be used.
Consider LOC tests in which the first vector V1 of a two pattern test <V1,V2>
is scanned in. In a design with two segments the first pattern is shifted in to the
segments one at a time as shown in Fig. 3.26 where the scan load cycles are shown
under SC. In non-segmented designs after scanning in V1 two capture cycles launch
and capture cycles are applied to the scan chain. For a two segment scan design one
can apply a capture cycle to segment 1 followed by a capture cycle to segment 2 as
showninFig. 3.27 a . In this case the capture cycle applied to segment 1 launches the
second vector V2 of the two pattern test which is comprised of the captured values in
segment 1 and the shifted in values in segment 2 of V1. The capture cycle applied to
segment 2 captures the test response and no test response is captured in segment 1.
Other possibilities of launch and capture for two pattern tests are shown in Fig. 3.27 .
In Fig. 3.27 e both segments are simultaneously applied launch and capture cycles
which amounts to be the same as in the case of unsegmented scan. Since there
are many different launch and capture scenarios which increase in number with
increasing numbers of segments many tests not possible using unsegmented can
be applied. Thus, higher delay fault coverage can be obtained in segmented scan
designs. The following example from Zhang et al. ( 2007 b ) illustrates this.
Consider the sequential circuit with two flip-flops shown in Fig. 3.28 a . The set
of TDFs in this circuit are shown on the right in Fig. 3.28 a . The two copies of the
circuit shown in Fig. 3.28 b through d represent the two time frame iterative logic
array used to generate two pattern LOC tests. If a single unsegmented scan chain is
used, the four TDFs on the right of Fig. 3.28 b cannot be detected. However, if a two
segment design is used with SC i in segment i, i D 1, 2, then the following faults
are not detected. Using launch off segment 1 and capturing in both the segments
the three faults shown on the right of Fig. 3.28 c are not detectable. Using launch off
segment 2 and capturing test response in both the segments one fault shown on the
right of Fig. 3.27 d is not detected. It should be noted that the fault coverage with
a given launch method can be achieved either capturing in both segments or in a
single segment as long as responses are captured in both segments by the tests used.