Models for Delay Faults - Models in Hardware Testing - page 92

0
1

D Q D Q

SD

Clock

GSEN

LSEN

Fig. 3.20 LTG cell

…

LTG

…

LSEN

Fig. 3.21 A scan chain with an LTG cell inserted

D in

0
1

DQ

S in

TMC

S CL

Fig. 3.22 DTS flip-flop

in Fig. 3.23 . The global scan enable signal SE changes to 0 after the initialization
cycle. However the local scan enable signal TMC of each scan cell changes to 0 on
the leading edge of the launch cycle. Thus during the launch cycle the scan chain is
shifted to generate the second pattern of the test.