Models for Delay Faults - Models in Hardware Testing - page 91

probability density functions have also been proposed ( Pramanick et al. 1992 ; Shao
et al. 2002 ; Lin et al. 2006 ). A metric proposed for the case where Pr (s) is not
known is called delay test coverage (DTC) ( Lin et al. 2006 ) giveninEq. 3.5 given
below. DTC can also be used with any test clock period Tc.

X ! . N

DTC D Max . tr /= Max . dr / (3.5)

r2F

3.3 DFT Techniques

In this section design for test (DFT) techniques proposed recently to reduce design
effort for LOS test method and methods to increase delay fault coverage are dis-
cussed. In Section 3.3.1 two methods to reduce the design effort for LOS designs are
discussed. Both these methods do not require any additional global signals and use
only the signals already available in MUX-scan designs. In Sections 3.3.2 a method
to increase delay fault coverage using multiple scan enable signals is outlined. In
Section 3.3.3 achieving higher delay fault coverage using segmented scan designs is
discussed.

3.3.1 LOS Testing Using Slow Scan Enable

As pointed out in Section 3.1.4 , for MUX scan LOS tests require scan enable line to
switch fast from 1 to 0. This is typically achieved by pipeline design for distributing
scan enable line which has high design time overhead and area overhead. In Ahmed
et al. ( 2007 ) a method to locally generate fast scan enable signal from a slow scan
enable signal has been proposed. The method adds one or more additional cells
called LTG cell, shown in Fig. 3.20 , to each scan chain as illustrated in Fig. 3.21 . In
Fig. 3.20 SD is the scan data, GSEN is the global slow scan enable, and LSEN is
the fast scan enable signal. Each LSEN drives the scan enable signals of a subset
of scan cells which are close to it. When the initialization pattern is scanned in,
the flip-flops in the LTG cell, which are part of the scan chain, are loaded with 01.
GSEN is changed to 0 after initialization phase as for LOC test. However the LSEN
signals which drive the scan cells changes only on the leading edge of the launch
cycle. Thus during the launch cycle LSEN is 1 thus the second pattern of the test is
obtained by a shift of the first pattern as required for LOS tests.
An alternate method to generate a fast scan enable signal proposed in Xu
et al. ( 2007 ) replaces each scan cell by, what is called, a DTS flip-flop shown in
Fig. 3.22 . InFig. 3.22 the select input of the multiplexer in the scan cell is driven
by the Timed Multiplexer Control (TMC) signal. TMC is the fast scan enable signal
in this design. The timing waveform for the operation of DTS flip-flop is shown