Models for Delay Faults - Models in Hardware Testing - page 90

Max(dr) and let the maximum of the delays of the paths through r used to detect the
fault by tests in S be Max(tr). The slack of line r slack.r/ D Ts - Max(dr) and let
the test slack of line r be testslack.r/ D Tc - Max(tr). Typically Tc is larger than Ts.
A delay defect of size greater than or equal to slack(r ) is detectable while the given
test only detects delay defects of size greater than or equal to testslack(r ). If the
fault is not detected testslack(r ) is defined to be infinity. Let the probability density
function of defect sizes on line r be P r (s), where s is the size of the defect. One can
compute the coverage of defects on line r ,C r , by tests in S as given below:

Z 1

P r .s/ds Z 1
testslack .r/

C r D P r .s/ds (3.1)

testslack .r/

Note that if Ts D Tc and testslack(r) D slack(r) all defect sizes that are detectable at
r are detected by the tests in S and in this case C r is also 1. If the number of faults in
the set of faults F is N then the coverage of delay defects in the entire circuit, DDC,
can be computed as:

DDC D X
r2F

C r =N (3.2)

Note that DDC will be equal to 1 if for every fault p in the circuit coverage C p
is 1. Thus DDC is similar to the fault coverage metric typically used to report
the effectiveness of covering modeled faults by a test set. Equations 3.1 and 3.2
are obtained from the statistical delay fault coverage (SDFC) metric proposed in
Park et al. ( 1989 ) assuming that Tc and Ts can be different as assumed in Sato
et al. ( 2005 ) and that the circuit path delays are constants.
A difficulty in using the coverage metric in Eqs 3.1 and 3.2 is the need to know
the delays of sensitizable paths to compute slacks of fault sites. Instead one can use
maximum delay of the structural paths through circuit leads ( Park et al. 1989 ) which
are typically higher than sensitizable path delays. A tighter estimate of Max(dr)
could be obtained by determining the longest delay functionally sensitizable paths
that do not contain any (b,f) pairs discussed in the last section. Another metric, used
in the statistical delay quality model (SDQM), proposed in Sato et al. ( 2005 ) mea-
sures probability of not detecting delay faults using a given test set. Delay quality
of a test set for a given fault r is defined as:

Z slack .r/

DQ .r/ D P r .s/ ds (3.3)

testslack .r/

The delay quality of a circuit with respect to a given test set is:
DQ D X
r2F

DQ .r/=N (3.4)

DQ is an estimate of the probability that a chip that passed a given test set is defec-
tive. The metrics given in Eqs 3.1 through 3.4 require knowledge of the probability
density function of defects. Metrics that can be used without the knowledge of the