Hardware Reference
In-Depth Information
Tabl e 3. 4
TDFs detected by multi-cycle tests
Circuit
Max. Det.
Method
Det. Sngl.
Det. Mult.
S1423
2,488
LOC
2,239
2,450
LOS
2,412
2,488
LOC/S
2,476
2,488
S1488
2,770
LOC
2,529
2,728
LOS
2,211
2,770
LOC/S
2,694
2,770
S1494
2,794
LOC
2,548
2,753
LOS
2,225
2,794
LOC/S
2,718
2,794
S5378
6,961
LOC
6,412
6,428
LOS
6,522
6,960
LOC/S
6,899
6,961
S9234
10,698
LOC
9,517
9,687
LOS
9,882
10,698
LOC/S
10,608
10,698
S13207
15,379
LOC
12,489
13,193
LOS
13,377
15,333
LOC/S
14,895
15,367
S15850
18,403
LOC
13,535
14,920
LOS
17,176
18,343
LOC/S
17,752
18,385
S35932
56,446
LOC
54,599
56,257
LOS
56,446
56,446
LOC/S
56,446
56,446
S38417
49,544
LOC
48,761
49,039
LOS
48,560
49,544
LOC/S
49,487
49,544
S38584
58,979
LOC
55,129
56,811
LOS
56,118
58,963
LOC/S
58,060
58,979
Tabl e 3. 5
Six types of TDF tests
Activation
Propagation
Type of path
Sensitization
Type of path
Sensitization
Type-I
Single
SNRB
Single
SNRB
Type-II
Multiple
Functional
Single
SNRB
Type-III
Single/multi
Functional
Multi
SNRB
Type-IV
Single
SNRB
Single
WNRB
Type-V
Multi
Functional
Single
WNRB
Type-VI
Single/multi
Functional
Multi
WNRB
six types of tests are illustrated. Testable paths of largest delay are constructed by ex-
tending subpath(s) containing the fault site towards circuit inputs and circuit outputs.
