Future of Moore’s Law - Guide to Cloud Computing for Business and Technology Managers - page 521

Appendix: Future of Moore's Law
On April 19, 1965, Gordon Moore, the cofounder of Intel Corporation, pub-
lished an article in Electronics Magazine entitled “Cramming More Compo-
nents onto Integrated Circuits” in which he identified and conjectured a
trend that computing power would double every 2 years (this was termed as
Moore's law in 1970 by the CalTech professor and VLSI pioneer, Calvin Mead).
This law has been able to predict reliably both the reduction in costs and the
improvements in computing capability of microchips, and those predictions
have held true (Figure A.1).
In 1965, the amount of transistors that fitted on an integrated circuit could
be counted in tens. In 1971, Intel introduced the 4004 microprocessor with
2300 transistors. In 1978, when Intel introduced the 8086 microprocessor, the
IBM PC was effectively born (the first IBM PC used the 8088 chip)—this chip
had 29,000 transistors. In 2006, Intel's Itanium 2 processor carried 1.7 billion
transistors. In the next 2 years, we will have chips with over 10 billion tran-
sistors. What does this mean? Transistors are now so small that millions of
them could fit on the head of a pin. While all this was happening, the cost
of these transistors was also exponentially falling, as per Moore's prediction
(Figure A.2).
In real terms, this means that a mainframe computer of the 1970s that cost
over $1 million had less computing power than your iPhone has today. The
next generation of smartphone we will be using in the next 2-3 years will
have 1 GHz processor chips. That is roughly one million times faster than
the Apollo Guidance Computer. Theoretically, Moore's law will run out of
steam somewhere in the not too distant future. There are a number of pos-
sible reasons for this. Firstly, the ability of a microprocessor silicon-etched
track or circuit to carry an electrical charge has a theoretical limit.
At some point when these circuits get physically too small and can no lon-
ger carry a charge or the electrical charge bleeds , then we will have a design
limitation problem. Secondly, as successive generations of chip technol-
ogy are developed, manufacturing costs increase. In fact recently, Gordon
Moore said that each new generation of chips requires a doubling in cost
of the manufacturing facility as tolerances become tighter. At some point,
it will theoretically become too costly to develop the manufacturing plants
that produce these chips. The usable limit for semiconductor process tech-
nology will be reached when chip process geometries shrink to be smaller
than 20 nanometers (nm) to 18 nm nodes. At those nodes, the industry will
start getting to the point where semiconductor manufacturing tools are too
expensive to depreciate with volume production; that is, their costs will be so
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