Digital Signal Processing Reference
In-Depth Information
3.5
ISSR under non-ideal circumstances
The simulation results presented in Figure 3.7 did assume that unbounded pro-
cessing power is available to the receiver. The limited availability of computing
resources will force a trade-off between bit error rate performance, latency and
throughput efficiency. For example, reducing the number of iterations in the
issr algorithm could provide significant energy savings in a battery powered
system. The ber characteristics for different numbers of iterations have been
plotted in Figure 3.8. Remark that most of the processing gain of issr is al-
ready achieved during the first few iterations. The final number of iterations
depends on the price one is willing to pay to keep down the implementation
losses (il).
For example, suppose that our target ber is 1
/
10
3
. Only four iterations are re-
quired to achieve a coding gain of 2 dB and to cross the E
b
/N
c
=
5 dB boundary.
A further reduction of the il by another 2 dB is achieved by augmenting the
number of iterations to 12. This is a viable option, also in a battery powered
device. As was mentioned earlier, increasing the step size of the issr algo-
rithm speeds up the convergence process at the cost of the accuracy. This time
though, there is no penalty for slightly increasing the step size: the limited
BER
Available bandwidth fraction
F [%]
5
6
6
1
6
7
72
7
6
80
8
3
8
6
number of ISSR
iterations: none,
4, 8, 12, 24, 100.
10
−1
10
−2
2 dB
2 dB
10
−3
unprocessed signal.
hard decision decoding.
4
10
−4
8
12
24
10
-5
100
output ISSR decoder
after 100 iterations.
−2
−1
0
1
2
3
4
5
E
b
/N
c
[dB]
Figure 3.8.
Simulated performance of the issr decoder as a function of the
number of internal iterations. Most of the processing gain is
achieved during the first few iterations.
