Digital Signal Processing Reference
In-Depth Information
of the voltage headroom would force the designer to bias closer to the linear
region. This results in a higher distortion due to channel length modulation in
the parasitic output resistance of the transistor due to the ac voltage swing at
the output. Note that this effect is not visible if the output current of the tran-
sistor immediately forced in the low-impedance of a large capacitive load or in
the source terminal of a cascode transistor.
A second possibility for the designer is to maintain a constant power consump-
tion, while the width of the transistor is increased. The bias current is subse-
quently kept constant by a reduction of the overdrive voltage (
V
gs
−
V
T
). By
doing so, the transistor settings shift closer to the weak inversion region as a
result of which the small-signal gain (
g
m
) starts to increase. It should be noted
that the improvement of transconductance gain of the transistor is not necessar-
ily translated in a higher voltage gain: a high amount of feedback provided by
the degeneration resistor (which is defined by the
g
m
R
S
product) only increases
the loop gain of the local feedback mechanism. As a result, the linearity of the
resistively degenerated transistor will increase.
The reader should keep in mind that these findings are completely opposite to
conclusions that were made for the common-source amplifier stage: remember
that in the latter case (without degeneration), it was shown that the overdrive
voltage should be increased in order to obtain better linearity (Section A.1).
At first sight, it may seem somewhat strange to the reader that without addi-
tional power consumption, the linearity performance can be increased merely
by enlarging the transistor dimensions. This concern is indeed justified since
for a constant bias current, the quadratic transistor model indicates that the
transistor dimensions will rise faster than the advantage in terms of transcon-
ductance gain. Eventually, the frequency performance will collapse under the
heavy weight of parasitics due to the large transistor dimensions. More pre-
cisely, the cut-off frequency (
f
T
) of the transistor, defined by the
g
m
/C
gs
ratio,
drops to a level much lower than the maximum performance specified for a
particular technology.
Apart from a deteriorating
f
T
of the transistor itself, the increased gate-source
capacitance will have a much larger impact on the bandwidth when the am-
plifier is embedded in a practical application: in combination with the output
resistance of the previous stage which is driving the amplifier, the large capaci-
tive load between gate and source creates a pole in the gain characteristic of the
input signal source. This finding suggests that, for a fixed power consumption,
there is an inevitable trade-off boundary between bandwidth and linearity. The
previously described method to improve the linearity of a single transistor am-
plifier is only useful for low to moderate operating frequencies. Even worse,
since a single-stage amplifier can only provide a very limited transconductance
