Digital Signal Processing Reference
In-Depth Information
nVdd
Ways to increase linearity:
1. Increase V
GST
, reduce W/L
power ↑
gain constant
2. Increase V
GST
, W/L ↓↓
I
bias
r
bias
i
out
V
GS
+v
AC
C
load
r
o
power constant
gain ↓
Figure A.17.
In the basic cmos common source amplifier, there is an explicit trade-
off between linearity, gain and power consumption. Only nonlineari-
ties of the transconductance are taken into account, while the nonlin-
ear output impedance r
o
of the transistor (caused by channel length
modulation) is ignored.
A distinction is made between the signal of interest and the bias settings of
the circuit. In an analog design, a small ac-signal is commonly superimposed
on a larger dc signal, which is called the
operating point
of the transistor.
As a result, the signal that is applied to the second-order transconductance
characteristic of the transistor can be written as a combination of a fixed dc-
setting and a varying ac-part:
(
dc
+
ac
)
2
. If this characteristic is expressed
using the Taylor series equivalent, it becomes clear that the magnitude of the
second-order component is in fact independent from the operating point of
the transistor. The first-order argument, which represents the effective small-
signal gain of the transistor, is linearly proportional to the dc-biasvalue.Asa
consequence, the linearity performance of a single common-source transistor
stage can always be improved by increasing the gate-source overdrive voltage
(see Section A.1).
Depending on design-time decisions, this method of improving linearity has
inevitable consequences on the performance of the amplifier. For example
(Figure A.17), suppose that the overdrive voltage was increased without alter-
ing the physical dimensions of the transistor. An increase of the dc-overdrive
voltage results in a quadratic increase in drain current Equation (A.2) and thus
also in power consumption. The designer can also decide to keep the small-
signal gain (
g
m
) constant. This is achieved by an appropriate reduction of the
transistor width. The result is a constant
g
m
and only a linear increase of the
dc bias current. A final choice for the designer is to maintain a constant power
dissipation. The consequence however will be a decrease of the transconduc-
tance
g
m
Equation (A.3). Either way, this simple example shows that linearity
does not come for free and there is a well-defined trade-off between power,
gain and linearity performance.
