Digital Signal Processing Reference
In-Depth Information
If the source impedance is chosen equal to the gate resistance
r
g
and
the load impedance is perfectly matched to the small-signal output re-
sistance
r
ds
, the power gain
G
of this circuit can be calculated as (A.5):
g
m
r
ds
4
ω
2
r
g
C
gs
G
=
,
(A.5)
which can also be expressed using the cut-off frequency
f
T
as (A.6):
f
T
f
2
r
ds
4
r
g
·
G
=
(A.6)
The maximum frequency of oscillation is reached when the power gain
drops below 0 dB:
r
ds
r
g
f
T
2
·
f
max
=
[Hz]
(A.7)
Since a mos transistor operated in the saturation region is a
transconductance-mode device, this result is not surprising: the se-
ries gate resistance
r
g
, in combination with the gate capacitance
C
gs
,
produces a high frequency pole.
3
Beyond this frequency, the effec-
tive voltage that is available over the gate-oxide capacitor
C
gs
starts
to decrease, thereby setting a limit on the power gain-bandwidth
product (
f
max
). It follows that, for high-frequency performance, the
gate resistance should be as low as possible. For this reason, a low-
resistance salicided polysilicon layer
4
is formed above the gate of a
mos transistor.
Because a mos transistor in saturation is a voltage controlled current
source, more power is delivered to a higher load-impedance. This is
also found in Formula (A.7), since the maximum frequency of oscil-
lation increases for a higher load resistance
r
ds
. It also follows that,
depending on the
r
ds
/r
g
ratio,
f
max
may be higher or lower than the
cut-off frequency of the transistor. This is quite an interesting obser-
vation because it raises the question which parameter fits best for a
particular circuit setup.
The circuit of a basic multistage transconductance amplifier is shown in figure
A.1. Each of the identical stages is build around an nmos common source
3
Remark that, although it is omitted here, the resistance of the inversion layer itself also plays an important
role in the effective gate resistance.
4
Basically, this is a metal-silicide contact.