Digital Signal Processing Reference
In-Depth Information
analog cmos circuit design, this goal is typically achieved using two-stage
amplifier, of which the low-frequency gain is even more increased using cas-
coded or gain-boosted voltage amplification stages. Beyond this frequency, the
distortion performance drops off steeply, as is pointed out in Appendix A.2.
Unfortunately, the bandwidth of the feedback-oriented approach is somewhat
limited. This is because a high voltage gain at a certain circuit node is always
accompanied by high node impedances, which in turn leads to a lower cut-off
frequency of the open-loop system. For medium to high-speed applications,
which operate in the frequency range between the first pole of the active el-
ement and the first pole of the closed-loop system, the simultaneous increase
in the dc-gain and reduction of the open-loop bandwidth will not lead to an
improved distortion suppression. The reason for this is that the performance of
such systems is commonly expressed using the
effective resolution bandwidth
(erbw), which takes into account that the amplifier must achieve the required
linearity performance, even at the maximum frequency-of-interest. However,
exactly the lack of excess gain at higher frequencies make the feedback ampli-
fier unsuited for application in, for example, the vga of the pulse-based radio
receiver in Chapter 6.
This chapter tries an unconventional approach, by compensating the nonlinear
transconductance of the cmos gain pair with a nonlinear load. In this amplifier,
the current-to-voltage conversion step at the output is performed by an active
load, which has the same transfer characteristics as the gain element. It was
shown that, for certain settings of the operating point of the gain- and the load-
transistors, the third-order harmonic distortion of the nonlinear loaded ampli-
fier can be completely cancelled by this approach. Since the exact settings for
optimal distortion performance depend on several parameters, such as the par-
asitic output resistance and the matching parameters of the underlying cmos
technology, calibration is a crucial factor for the performance of the proposed
amplifier.
Suggestions for improvements
In the current implementation of the standalone open-loop amplifier, the chip
directly drives the 50
load impedance of the measurement setup. This in
contrast to an amplifier that is embedded in a system and only drives the ca-
pacitive load of an on-chip ad converter. In the former case, however, the linear
current-voltage characteristic of the linear output impedance leads to the regen-
eration of distortion components in the very last stage of the multistage ampli-
fier. This may mask the true capabilities of the open-loop approach. A much
better approach is to measure the performance of the amplifier in an embed-
ded application, where the wideband buffer stage at the output is replaced by
