Digital Signal Processing Reference
In-Depth Information
As a result of the difference between the transistor parameters, third-order
distortion components will reappear at the output of the amplifier. It is now
interesting to predict what can be expected in terms of linearity performance,
when some realistic mismatch values are taken into account. In order to have
some reference data, first of all the effect of mismatch on a simple resistive
loaded differential pair is recapitulated. Then, without going into the gory de-
tails of the sensitivity calculations, the mismatch results of the nonlinear loaded
amplifier are introduced, followed by a quantitative evaluation of the results.
Mismatch versus distortion in a resistively loaded pair
Mismatch in a resistive differential pair
causes a dc offset in the current at the out-
put. At first sight this may not seem a very
important issue, but the difference in the op-
erating point between the branches of the pair
deteriorates the suppression of the common-
mode to differential conversion gain. More-
over, first-order mixing products between the
differential input and common mode noise
will upconvert this noise to the frequency
band of interest. Apart from offset, mismatch
in a resistive loaded differential pair will
cause second-order distortion to reappear, in addition to the existing third-order
components. The offset and second-order distortion expressions for the resis-
tive loaded pair are given by (7.10):
nVdd
V
cmfb-
V
cmfb
+
V
out-
V
out+
r
load
V
in+
V
in-
g
mi
g
mi
i
diff
I
gain
i
offset,
dc
I
bias
V
t
V
gs
−
=
V
t
3
16
·
v
idp
V
gs
−
V
t
V
gs
−
1
2
β
β
hd
2
=
V
t
+
,
(7.10)
V
t
additional reduction*
where
v
idp
is the peak amplitude of the differential ac-signal
v
id
over the
input terminals of the amplifier. Typical values for the standard deviation
of the matching parameters of an
nmos
device in a 0
.
13
μ
m process are
σ
0
,V
t
m. For example, suppose that
an uncertainty interval of 3
σ
is taken into account. The yield in this confi-
dence interval is thus 99
.
7%. Also suppose that the area of the transistors is
WL
=
3mV
· μ
mand
σ
0
,β/β
=
0
.
01
· μ
m
2
V
t
) is 130 mV. It follows that,
compared to a single-ended transistor amplifier, an additional hd
2
reduction
(*7.10) of at least 20 dB is guaranteed.
=
1
μ
and the overdrive voltage (
V
gs
−
