Digital Signal Processing Reference
In-Depth Information
less accurate and distortion levels will rise. Nonetheless, since the core cell
amplifiers are at least an order of magnitude faster than the cut-off frequency
of a higher-order feedback system, a remarkable good distortion suppression
is still achieved at frequencies where most closed-loop amplifiers are only a
shadow of their former selves.
7.4
Distortion analysis of the nonlinear loaded stage
In the previous section, it was intuitively demonstrated that third-order dis-
tortion in the open-loop amplifier topology of Figure 7.2 could be suppressed
thanks to the inverse characteristics of the diode-connected differential load. It
was also cleverly observed that the signal swing at the output of the average
amplifier is larger than the swing at its input. Thus, in order to remain good dis-
tortion suppression performance for gains larger than unity, the transconduc-
tance characteristic of the loading pair had to be linearized by means of a larger
overdrive voltage. This goal was achieved by maintaining the same tail current
for both the gain- and loading pair. In this section, it is mathematically shown
that for the simple quadratic transistor model, third-order distortion completely
disappears when the tail current of the gain pair is chosen equal to the tail cur-
rent of the load. For the more general case, where the transconductance of the
transistor deviates from the idealized quadratic model, either towards a more
linear or a higher order characteristic, a mathematical proof would not bring
additional insight in the matter due to the high complexity, but the insights
brought by the calculations hereunder should remain valid.
In the mathematical solution below, the quadratic
g
m
characteristic from
[Lak94] has been used. The large signal model of an nmos in strong inversion
depends on some physical parameters represented by
K
n
, its dimensions w (ef-
fective gate width) and l (channel length) and the overdrive voltage
V
gs
−
V
t
in the following way (7.1):
K
n
W
V
t
)
2
I
=
L
(V
gs
−
β
2
(V
gs
−
V
t
)
2
=
(7.1)
Our first target is to find an expression for the transconductance when the tran-
sistors are embedded in a differential pair. It is clear that due to the symmetrical
setup, even-order components will disappear from the transfer characteristic.
In case of an ideal current source
I
bias
forcing a constant bias current through
the transistor pair, the following equations hold (7.2):
i
od
=
i
noutp
−
i
noutn
(differential current)
I
bias
=
i
noutp
+
i
noutn
(common mode current)
(7.2)
