Digital Signal Processing Reference
In-Depth Information
One of the dividers is part of a fixed 1:64 postscaler section (Figure 6.1), which
is used to keep the baseband section of the receiver alive. The second divider
is used as dummy ballast for the remaining output nodes of the high-speed
prescaler. Failing to do this puts an unequal load on different outputs of the
prescaler. This would result in i/q imbalance errors between the 0
◦
/180
◦
and
the 90
◦
/270
◦
inputs of the quadrature downconversion mixer. The output of the
1:64 postscaler
2
is further fed into a 3-bit programmable divider. The signal
of this divider forms the heartbeat of the receiver and controls all time-critical
functions, including timing of the receive window circuitry.
Before being further distributed to the different subcircuits, the heartbeat clock
is converted to a multiphase clock signal. For this purpose, the output of the
programmable divider is buffered by four parallel interconnected delay blocks.
The delay blocks can be programmed independently from each other to delay
the heartbeat clock between
d
0
and
d
0
+
3 ns. The clock delay itself is ac-
complished in an analog manner, by varying the load between the outputs of
a differential pair. The load itself formed by the 1
/g
m
impedance of a diode-
connected mos transistor, the current through which is controlled by the output
voltage of a 4-bit on-chip da-converter (Figure 6.3). In this way, the phase shift
nVdd
Adjustable current source
controls current ratio (a / b).
Vadj
4-bit DAC
Diode-connected transistor.
Output impedance: 1/g
m
~1k.
a
b
On-chip DA
converter
out_n
clock_outn
125fF
Cross-coupled capacitors to
equalize parasitics to gnd.
clock_outp
out_p
125fF
clock_inp
clock_inp
107/54/27 MHz
clock_inn
clock_inn
Edge reconstruction:
regenerative latches
Vbias
nGND
Figure 6.3.
A single delay subcell of the multiphase clock generator. Four of these
precision analog delay cells work in parallel in order to generate four
independently controllable clock phases. The mutual delay between the
first two phases marks the start- and stop-time of the receive window.
2
The nominal operating frequency of the receiver is 6
.
85 GHz. The output of the 1:64 fixed postscaler yields
the 107 Msymb/s sampling speed mentioned in the introduction of this section.
