Digital Signal Processing Reference
In-Depth Information
Chapter 6
REFERENCE DESIGN
OF A PULSE-BASED RECEIVE UNIT
The last section in this topic provides a more technical discussion of the
implementation details (and problems) of a fully integrated front-end of a
pulse-based receive unit. In the full-scale implementation of the system, sev-
eral of these modules would work together in parallel. They form the backbone
of the pulse-based radio system which has been discussed throughout the pre-
vious chapters. The wideband receiver front end is intended for use in the 3
.
1
to 10
.
6 GHz band which was released by the fcc early in 2002 for use by
so-called
ultra-wideband
(uwb) radio devices.
The receiver was implemented in a main-stream 0.18
μ
m standard
cmos
technology without any particular
rf-enhancements. Incorporated in the
1
.
4mm
2
chip are (1) a mixed-signal multiphase clock generator which
concerts the interactions between different subsystems, (2) a mixer/pulse-to-
baseband converter and (3) a baseband amplification chain. The dual in-phase/
quadrature (i/q) signal path of the receiver allows for coherent demodulation
of phase modulated pulse-based radio signals. The design is optimized to cope
with the large bandwidths at the rf-input stage and the baseband output buffers
are able to directly drive an external analog-to-digital converter or measure-
ment equipment. Three selectable sampling speeds are available in the receiver,
supporting a maximum symbol rate of 107 Msymb/s. The entire system, which
includes the clock drivers and the output buffers, consumes 120 mW from a
single 1
.
8 V power supply.
The block diagram of the pulse-based wideband radio receiver is shown in
Figure 6.1. Remark that the architecture is very similar to the signal chain of a
(zero-if) quadrature heterodyne receiver. The most significant distinction with
the traditional receiver architecture is formed by the gating circuit located in
front of the receive chain. The receive window has two different tasks, each
1
.
4
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