NANOSCALE DEVICES: APPLICATIONS AND MODELING - Bio-Inspired and Nanoscale Integrated Computing - page 45

Source Gate Drain

N N

Channel

P

Figure 2.9. Schematic representation (side view) of an MOS FET (N-channel type).

with higher resolution or new methods of fabrication. But there are other types of
nanodevices that are ''nano'' by nature without the need for us to try to make
them smaller. This section reviews some of these devices.

2.4.2.1. Nanoscale Field-Effect Transistors. Let us recall from Chapter 1
the operation of a metal-oxide-semiconductor field-effect transistor (MOS FET),
shown schematically in Figure 2.9. Conduction in this device happens between
source and drain in a channel below the gate. The properties of this channel can be
modulated by the voltage applied to the gate (by attracting more charge carriers to
the channel or pushing them away from it), and this is the basis of the switching
action of the transistor.
Now let us focus more on the channel itself. We introduced nanowires and
nanotubes earlier in this chapter. The basic idea behind nanoscale FETs is the use
of a nanowire or nanotube as the conducting channel of the transistor. This wire
or tube is connected between two electrodes (source and drain), and a third
electrode placed in close proximity (above, below, or even on its side) acts as gate
(Fig. 2.10). The difference with traditional MOS devices is that here transport does
not happen in a 3D bulk material, but rather in a 1D structure, which is radically
different. As a result, these nanoscale FETs can have major differences in
characteristics from their traditional counterparts, including several advantages.
In these 1D structures or quantum wires, charge carriers are confined in the
two lateral directions and behave completely differently compared to 3D materi-
als: not only do they experience strong energy quantization effects, but their
movements are strongly correlated with each other. In particular, carriers in these

Gate

Source Drain

Nanotube channel

Silicon substrate

Figure 2.10. Schematic representation (side view) of a nanotube FET.