CONCLUDING REMARKS AT THE BEGINNING OF A NEW COMPUTING ERA - Bio-Inspired and Nanoscale Integrated Computing - page 539

process digitally or in analog. The chapter also discussed a hierarchical architec-
ture that overcomes the short attenuation length of spin waves. More information
about this research can be found at the Bio-Inspired and Nanoscale Integrated
Computing Research Group at the University of California, Los Angeles, http://
www.seas.ucla.edu/

eshaghia/lab_web/index.htm, and the Center on Functional
Engineered Nano Architectronics, http://www.fena.org/.
Chapter 8 discussed parallel techniques that exploit the wave properties of the
spin-wave architectures discussed in the previous chapter. It discussed a set of
general algorithmic techniques, including finding the maximum/minimum,
first/last of a list, prefix sum, and shifting elements of a list. It also discussed
routing through the three architectures: reconfigurable mesh, crossbar, and fully
interconnected cluster. The fault tolerance feature of routing with spin waves
was also described. More information about this research can be found at the
Bio-inspired and Nano-scale Integrated Computing Research Group at the
University of California, Los Angeles, http://www.seas.ucla.edu/

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B eshaghia/lab_

web/index.htm.
After the introduction to spin waves and its parallel techniques in previous
chapters, Chapter 9 showed how a variety of fundamental operations would work
using spin waves. The chapter first discussed the operation of digital-to-analog
conversion, used in many of the following operations. It then described full
adders, multipliers, basic logic gates, decoders, encoders, multiplexers, and
demultiplexers, priority encoders, and shifters. Being able to describe this variety
of functions shows that nearly any logic function, which would be a combination
of these basic operations, can be realized using spin waves. More information
about this research can be found at the Bio-Inspired and Nano-scale Integrated
Computing Research Group in the University of California, Los Angeles, http://
www.seas.ucla.edu/

eshaghia/lab_web/index.htm.
To conclude the discussion of nanoscale integrated circuits, Chapter 10
explored fault tolerant computing. The chapter first discussed problems that arise
from consistenly shrinking the feature size of devices—nanoscale devices will
inevitably have permanent defects as well as transient errors. It described three
major ways to perform reliable computations despite these faults: structural
redundancy, information redundancy, and reconfigurability. It also covered a
variety of ways to evaluate the reliability of fault-tolerant devices. More
information about this research can be found at the Formal Engineering Research
with Models, Abstractions and Transformations Lab at Virginia Tech, http://
fermat.ece.vt.edu/.

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20.1.2. Bio-Inspired Models and Applications
In Part II, we turned our attention to biologically inspired models and applica-
tions of nanotechnology. Chapter 11 covered a variety of approaches for
molecular devices. The chapter first described some approaches to creating
molecular switches and memory devices. It then proceeded to discuss circuit
and

architecture level molecular integration, particularly electrostatic