BIOMIMETIC CORTICAL NANOCIRCUITS - Bio-Inspired and Nanoscale Integrated Computing - page 473

Equation 17.8 sums the connections from the first available layer m+1 to
layer j.

4 5

H 2 E þ P

j 1
i ¼ 1 ð D i þ L i Þ D j

C total ¼ 4 X

n

ð 17 : 8 Þ

D j þ S j

j ¼ m þ 1

A rudimentary calculation using a neuron without learning capabilities
shows that less than 6000 connections can emerge from the projected area of
a single neuron, 62.5 square microns in the year 2021. If each neuron has 10,000
synapses, and an axonal fanout of 10,000, this projected neural area cannot
support the number of necessary point-to-point connections. Adding learning
capabilities to the neuron effectively increases the size of each synapse (and
ultimately the entire neuron) by a factor of 10 in the extreme case [79]. This size
increase provides many more locations to place interconnections on the surface
of the neuron, but the interconnections possible are limited by the number of
metal layers.
Even if the die is mounted so that a second die is flipped 4 onto it, and 3D
interconnections are made [81], the vertical connections between the dies are so
large with current technologies that the number of additional connections is
relatively small. Assuming a flip-chip design, the connections of the flip-chip
design consist of two types of connections: One is the connections horizontally on
the chip outside the core; another is the interconnections between two chips, one
flipped. Vertical windows are used to indicate those windows for connecting to
the second die. Horizontal windows are for those wires used to communicate
between two cores on the same die. We apply the Pyramidal model for the out-
going connections. There are two key terms that we are going to use for this
model. Figure 17.10 shows one side of a flip-chip. The outer area of the flip-chip
is assigned to the horizontal windows. The central area of the flip-chip is assigned
to the vertical windows. The purpose for interconnections both laterally and off-
chip vertically is to maximize the number of connections to the core. In order to
achieve this, the way we assign these two types of windows is to maximize the
number of horizontal windows with available metal layers and utilize the
remaining space for windows which are used for the vertical interconnections
between two chips.
The ninth equation computes the possible intercore intrachip (horizontal)
connections on available metal layers. The tenth expression, an inequality, is a
constraint on the parameters, and when it holds Equation 17.11 can be applied to
compute the number of vertical connections possible to the core using a flip-chip
approach.

4 Flip-chip technology implies that two dies are joined face-to-face, with vertical connections between
the two dies.